Re: [vhdl-200x] VHDL Testbench Enhancements

From: <wallacerim_at_.....>
Date: Mon May 21 2007 - 14:34:04 PDT
Jim Lewis wrote: 
> Hi, 
> The VHDL standards community has been considering whether 
> to enhance VHDL to add advanced testbench features. 
> > If you are a VHDL user, 
> Do you want these features added to VHDL? 
> Would you rather adopt a verification language that 
> already supports these (SystemVerilog, SystemC, E, Vera). 
> > I think VHDL needs to enhance testbench capability to 
> stay competitive. 

Looking at the proposals from both the long term (I was at AFWAL as the Project Engineer that gave birth to VHDL, I took over from Al Dewey and brought the language out of the Lab to the IEEE) and the short term (as a design engineer at Northrop Grumman) I do not see a reason to have one language cover all elements of both HDL and test/verification scripting.
My answer is: No, don't do this.
If anything needs to be done it is to open any number of scripting languages to handle the proper temporal, typed interfaces.
My industry does not want a language that resembles: "One Ring to rule them all, One Ring to find them, One Ring to bring them all, and in the darkness bind them."   What we do want is clear escapes from one form to another allowing the right tools to be used at the right times.  I can't imagine any good coming from a mash-up of different lexical and semantic issues from a disjunct of purposes expressed in one highly bastardized syntax.
We buy large installations of tools and we have lots of them rotting in the pile due to their cumbersomeness, lack of true utility and other such.  We'd rather have a tool set that does it's job well and can flow from one tool to another.
Richard Wallace
Northrop Grumman 

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Received on Mon May 21 14:34:38 2007

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