Hi,
I have been working on VHDL standardization in recent years and I am
also working on subcommittee of the SystemVerilog IEEE standards effort
dubbed SV-XC. It's goal is to formalize mixed language
interoperability between SystemVerilog, VHDL, System-C, and
Verilog-AMS. The perspective of the effort is SystemVerilog and the
specifications that result are aimed at the SV LRM. Nevertheless,
language changes may be proposed for and brought to other language
groups that benefit interoperability. There are current discussions
about language enhancements to VHDL and this SV effort is orthogonal to
that. It is no coincidence that both efforts are active concurrently
as they represent different takes on satisfying the unmet needs of our
user community.
The first step in the SV effort is gathering requirements and
priorities broadly. The SV-XC committee is soliciting your input on
SystemVerilog Interoperability. The committee has prepared a survey in
order to gather user requirements and help focus the standardization
activities based on your requirements. The survey is available at:
http://www.eda-stds.org/sv-xc/otherdocs/survey1.0.txt
This is a simple text file. You can save it on your desktop and fill it out with your normal editor.
The instructions are provided in the survey. Please send your feedback to the committee by emailing to sv-xc@eda.org. If you like you can also send your completed survey to logie@synopsys.com or somdipta@ti.com, the co-chairs of SV-XC.
Regards,
John Shields
Mentor Graphics
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Received on Wed Apr 4 10:29:29 2007