RE: [vhdl-200x] Review of FT-32

> I don't think this is possible.  If it is not possible to 
> detect wether
> Design.E(A).C2.E2.p1 is an error, then you don't know its 
> type too.  Then
> you can't analyze any expression containing such an expanded name.

[and similar interesting comments on how the analyzer can
or cannot determine the type of an expanded name]

It occurs to me that there may be a rather attractive solution
to this.  Suppose we forbid any use of hierarchical names
EXCEPT in an alias definition, thus:

  alias hier_ref: std_logic is TB.design(D).block(A).sig;

Now we can use "hier_ref" with confidence in the current
design unit, its (sub??)type being fully defined.  Analysis
is then not an issue.  At elaboration time, all required
checking is clearly determined by the alias definition.

The more I look at this the more I like it.   Only rarely
will it be more verbose than the Verilog-like
"use a hierarchical name anywhere" equivalent, and it
nicely separates analysis-time and elaboration-time 
checking in the same way that components do.

It also opens the door to the clean encapsulation of 
a collection of such out-of-scope references by means of
something akin to SystemVerilog's interface or clocking
constructs.

Alex's concerns about unresolvable cycles and nondeterminism
are unaffected by this idea, as it's only about syntax.
Also, I still believe that out-of-scope objects should be 
read-only, but that opinion is orthogonal to this idea
of using alias to tidy up the syntax.
-- 
Jonathan Bromley, Consultant

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