Françoise, Jim and all, I've made a quick pass over the VHDL-200x-FT proposals and the ISAC issues to determine whether they affect the VHPI specification - see the "Affects VHPI" column on each of the sheets in the attached. Perhaps we can use this as a starting point for discussion next week. Cheers, PA -- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106 > -----Original Message----- > From: owner-vhdl-200x-ft@eda.org > [mailto:owner-vhdl-200x-ft@eda.org] On Behalf Of Francoise Martinolle > Sent: Friday, 25 March 2005 04:29 > To: 'Jim Lewis'; 'VHDL-200x'; vhdl-200x-ft@eda.org > Subject: [vhdl-200x-ft] RE: [vhdl-200x] Meeting Notice: VHPI > Impact VHDL-200X-FT proposals Monday March 28 > > > > Jim, > > Do you have a list of the ft proposals which have an impact > for VHPI? Any information you may have would be useful for > the VHPI tech team to review in advance of Monday's meeting. > Have you written down any VHPI proposed enhancements? > > Thanks > > Francoise > ' > > -----Original Message----- > From: owner-vhdl-200x@eda.org > [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis > Sent: Monday, February 28, 2005 9:30 PM > To: VHDL-200x; vhdl-200x-ft@eda.org > Subject: [vhdl-200x] Meeting Notice: VHPI Impact VHDL-200X-FT > proposals Monday March 28 > > Next VHDL-200X-FT Review Meeting: > Monday, March 28, 2005 > 2-4 PM PST > > Please review the IEEE pat policy before the meeting: > http://standards.ieee.org/board/pat/pat-slideset.ppt > > Dial in information > 888-742-8686 > 303-928-2600 (int'l) > Conference ID: 4737027 > > Agenda: > Review VHDL-200X-FT proposals and discuss their impact > on VHPI with the VHPI team. > > Regards, > Jim > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Jim Lewis > Director of Training mailto:Jim@SynthWorks.com > SynthWorks Design Inc. http://www.SynthWorks.com > 1-503-590-4787 > > Expert VHDL Training for Hardware Design and Verification > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >
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