RE: [vhdl-200x] Draft PAR

From: Jim Lewis <Jim@synthworks.com>
Date: Mon Jun 28 2004 - 12:27:14 PDT

OOPs I missed one of the typo amendments. Let me
restate my motion to amend the motion:

I move that we amend the motion for the approval of the
PAR so that it reads as follows:

    That the VASG approve the attached revision PAR for IEEE Std 1076 with
    the following changes:

      Item 11: Strike out the word "Entity" and insert the word "Individual".

      Item 13: Change "1164 and 1076.2" to "1164, 1076.2 and 1076.3".

      Item 13: Change releated to related.

      Item 16: Change P364 should be P1364 (Verilog).

Cheers,
Jim

-------- Original Message --------
Subject: RE: [vhdl-200x] Draft PAR
Date: Mon, 28 Jun 2004 12:03:10 -0700
From: Jim Lewis <Jim@synthworks.com>
To: VHDL-200x <vhdl-200x@eda.org>

I move that we amend the motion for the approval of the
PAR so that it reads as follows:

    That the VASG approve the attached revision PAR for IEEE Std 1076 with
    the following changes:

      Item 11: Change to "Individual".

      Item 13: Change "1164 and 1076.2" to "1164, 1076.2 and 1076.3".

      Item 16: Change P364 should be P1364 (Verilog).

Regards,
Jim

> Peter,
>
> I will second the motion.
>
> Regards,
>
> Dennis
>
> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Peter Ashenden
> Sent: Sunday, June 20, 2004 10:02 PM
> To: vhdl-200x@eda.org
> Subject: RE: [vhdl-200x] Draft PAR
>
> Folks,

Further to my previous message, I move the following:

    That the VASG approve the attached revision PAR for IEEE Std 1076 with
    the following changes:

      Item 11: Change to "Entity".

      Item 13: Change "1164 and 1076.2" to "1164, 1076.2 and 1076.3".

Cheers,

PA
(as a VASG member)

--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
PO Box 640                                   Ph:  +61 8 8339 7532
Stirling, SA 5152                            Fax: +61 8 8339 2616
Australia                                    Mobile: +61 414 70 9106
> -----Original Message-----
> From: owner-vhdl-200x@eda.org 
> [mailto:owner-vhdl-200x@eda.org] On Behalf Of Peter Ashenden
> Sent: Friday, 18 June 2004 22:28
> To: 'Bailey, Stephen'; vhdl-200x@eda.org
> Subject: RE: [vhdl-200x] Draft PAR
> 
> 
> Steve and colleagues,
> 
> Thanks to Steve for preparing the draft PAR.  I echo Edward's 
> reservations about mixed individual/entity balloting.  
> Providing entity voting as a form of recognition of support 
> doesn't really give any benefit to entities. Compare that 
> with entity-only balloting, where entities are on the 
> proverbial level playing field.  I think that is perceived as 
> being of higher value to entities, and would be more likely 
> to attract funding.
> 
> An important point to note is that if the ballot group and WG 
> are entity-based, the WG can still determine separate voting 
> rules for subgroups, such as technical teams.  Those subgroup 
> rules can admit of individual voting.  This might be a way of 
> satisfying people's concerns about disenfranchisement of 
> individuals in the technical work.
> 
> Cheers,
> 
> PA
> (as a VASG member)
> 
> --
> Dr. Peter J. Ashenden                        peter@ashenden.com.au
> Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
> PO Box 640                                   Ph:  +61 8 8339 7532
> Stirling, SA 5152                            Fax: +61 8 8339 2616
> Australia                                    Mobile: +61 414 70 9106
> 
> 
> > -----Original Message-----
> > From: owner-vhdl-200x@eda.org
> > [mailto:owner-vhdl-200x@eda.org] On Behalf Of Bailey, Stephen
> > Sent: Thursday, 10 June 2004 16:05
> > To: vhdl-200x@eda.org
> > Subject: [vhdl-200x] Draft PAR
> > 
> > 
> > Attached is a draft of the PAR.  Peter Ashenden (DASC Chair)
> > has already performed one review cycle and the attached 
> > includes comments from his review.
> > 
> > Note that I'm suggesting that we allow both individual expert
> > and organization entity membership for the working group.  
> > The membership of the WG needs to be discussed.  But, here's 
> > my thinking as well as an observation from Edward Rashba of 
> > iEEE SA on the options here:
> > 
> > 1.  We need to find financial support for the VHDL-200x work.
> >  Primarily the funds are needed for the focussed effort of 
> > editing the VHDL LRM.  I have received estimates for the 
> > costs of this work of ~$200k over the course of 2-3 years 
> > (two revisions of VHDL under VHDL-200x).
> > 
> > 2.  I have been informed that Accellera has spent at least
> > $150k to get the SystemVerilog 3.1a LRM to its current state 
> > with possibility that a bit more funding will be needed to 
> > complete the IEEE standardization process.  Therefore, the 
> > estimates for VHDL are within the general ballpark given the 
> > expected scope of LRM editing anticipated.  Hopefully, no one 
> > should expect that VHDL can do this work at a significant 
> > discount to that which was needed for SystemVerilog.
> > 
> > 3.  Corporate support of our work as expressed by funding for
> > the effort is a great indication that we are doing something 
> > that users need (and EDA vendors recognize users want).  
> > Therefore, funding is a positive and we should be soliciting it.
> > 
> > 4.  Therefore, I thought that we could allow both membership
> > classes for 1076.  Although it has not been officially placed 
> > to a vote of the WG, I heard feedback that the current 
> > members wanted to stay with individual membership.  Allowing 
> > organizational entity membership would allow us to also 
> > recognize corporate support for our work by giving supporters 
> > a direct voice in the WG.
> > 
> > 5.  Edward Rashba counseled against having both membership
> > classes.  However, he also indicated that in some cases, such 
> > as ours, it has and could work.  Our historical operation 
> > makes it reasonable to believe that supporting both 
> > membership classes for 1076 could work.
> > 
> > 6.  Personally, I believe individual only membership would
> > hinder the ability of the WG to successfully solicit 
> > financial support.  However, I will do my best to find the 
> > funding whatever membership option the WG decides to use.
> > 
> > Since <24 hours is insufficient time to review a PAR and
> > comment, no vote to approve the PAR will be held tomorrow (10 
> > Jun 04 Meeting).  However, we will entertain discussion on 
> > the topic in preparation for a future vote via email to be 
> > conducted in ~2 weeks time.  (Discussion via email is also welcome.)
> > 
> > I'm looking forward to the meeting.  I think that Erich's
> > work on defining how PSL can be incorporated in VHDL by 
> > reference combined with the VHPI and other language change 
> > proposals that appear ready to go will result in a new 
> > revision that is highly valuable.  It will also lay the 
> > foundation for even more capabilities in the next revision.
> > 
> > To review the proposals visit
> > www.eda.org/vhdl-200x/vhdl-200x-ft 
> <www.eda.org/vhdl-200x/vhdl-200x-ft> 
> 
>  <<tmp113842779_9644.html>> 
> ------------
> Stephen Bailey
> ModelSim Verification TME
> Mentor Graphics
> sbailey@model.com
> 303-775-1655 (mobile, preferred)
> 720-494-1202 (office)
> www.model.com <www.model.com> 
> 
> 
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

1. ASSIGNED PROJECT NUMBER: 1076

2. SPONSOR DATE OF REQUEST: 2004-06-11

3. TYPE OF DOCUMENT: Standard

4. TITLE OF DOCUMENT: IEEE Standard VHDL Language Reference Manual

5. LIFE CYCLE: Full-Use

6. TYPE OF PROJECT: Revision 1076-2002

Modified PAR?
In Ballot? No

7. WORKING GROUP INFORMATION

Name of Working Group: VHDL Analysis and Standardization Group (VASG) a.k.a VHDL-200x Project
Approximate Number of Expected Working Group Members: 30

8. CONTACT INFO FOR WORKING GROUP CHAIR

Name of Working Group Chair: Stephen Bailey
Telephone: 303-775-1655
FAX: 303-652-1578
E-mail: sbailey@model.com

9. CONTACT INFO OF CO-CHAIR/OFFICIAL REPORTER

Name of Co-Chair/Official Reporter: Peter Ashenden
Telephone: +61 8 8339 7532
FAX: +61 8 8339 2616
E-mail: peter@ashenden.com.au

10. CONTACT INFO OF SPONSOR

Sponsor: C/DA
Name of Sponsor Chair: Peter Ashenden
Telephone: +61 8 8339 7532
FAX: +61 8 8339 2616
E-mail: peter@ashenden.com.au

Standards Coordinator (Power Engineering Society Only):
This is the information you entered:
  Name:
  Telephone:   Fax:
  E-mail:
This is the information in our database: Check The Box To Use This Information
  Name:
  Telephone:   Fax:
  E-mail:

CO-SPONSOR INFORMATION (THIS IS BEING SPONSORED BY TWO SPONSORS):
Cosponsor:
Name of Cosponsor Chair:
Telephone:
FAX:
E-mail:

Standards Coordinator for Cosponsor (Power Engineering Society Only):
This is the information you entered:
  Name:
  Telephone:   Fax:
  E-mail:
This is the information in our database: Check The Box To Use This Information
  Name:
  Telephone:   Fax:
  E-mail:

11. TYPE OF SPONSOR BALLOT: Mixed

Expected Date of Submission for Initial Sponsor Ballot: 2005-01-31

12. PROJECTED COMPLETION DATE FOR SUBMITTAL TO REVCOM: 2005-06-30

13. SCOPE: This project will revise and enhance the VHDL LRM by including a standard C language interface specification; specifications from previously separate, but releated standards 1164 and 1076.2; and general language enhancements in the areas of design and verification of electronic systems.

Completion of this document contingent? No

14. PURPOSE: The VHDL language was defined for use in the design and documentation of electronics systems. It is being revised to incorporate capabilities that will improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, will simplify the maintenance of the specifications.

14a. Reason: General language enhancements improve designer productivity by allowing the specification of models more efficiently or the ability to specify functionality that was previously not possible or impractical to specify in VHDL. Verification capabilities are needed to improve the quality of the designs and to address the significant and growing portion of the electronic system design schedule that is being spent in ensuring the design is functionally correct before manufacturing. These capabilities directly address productivity and quality. Additional capabilities are being added to facilitate standard interfaces for tool interoperability.

15. INTELLECTUAL PROPERTY:

Patent Policy: Yes
Copyrights: Yes   The working group has benefitted from technology donations from EDA companies. These donations have been accompanied by letters of donation with signatures of authorized officials from the donating companies.
Trademarks: No  
Registration of Object: No  

16. SIMILAR SCOPE: Yes

Explanation: P364: Standard for Verilog Hardware Description Language. There is significant overlap between the capabilities of the two languages. However, both have proven to be accepted in the marketplace with multiple tools supporting one or both languages and with many users that use one or both languages. P1647 Standard for the Functional Verification Language 'e': Some proposed language enhancements in the area of verification will overlap capabilities that may eventually be standardized through this working group. P1800 Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language. This is a proposed effort to extend the capabilities of Verilog. As the market needs better design and verification capabilities, it is natural that both VHDL and Verilog would be working to meet those market requirements for their users.
Sponsor: CS and CAG
Project Number: See above
Project Date:
Project Title:

17. FUTURE ADOPTION - INTERNATIONAL SPONSOR: Yes

Int'l Organization: IEC 93 2
Int'l Contact Person: Alex Zamfirescu
Telephone:
FAX:
E-mail: azro@onebox.com

18. FOCUS ON HEALTH, SAFETY OR ENVIRONMENTAL ISSUES:

Explanation:

19. ADDITIONAL NOTES: Item 9. Peter Ashenden is the document custodian. The WG chair, vice chair and secretary are responsibile for all other duties. Item 13. Previously, part of this work has been conducted under the P1076b PAR. When that work started, only new capabilities were proposed to be added to VHDL in the form of a C language interface for tools. The WG has decided additional enhancements and revision of the standard are required. Therefore, this PAR is being submitted to supersede the P1076b PAR and that work will be subsumed under the broader scope of this PAR.

I acknowledge having read and understood the IEEE Code of Ethics I agree to conduct myself in a manner which adheres to the IEEE Code of Ethics when engaged in official IEEE business.

The PAR Copyright Release and Signature Page must be submitted either by FAX to 208-460-5300 or as e-mail attachment in .pdf format to the NesCom Administrator before this PAR will be sent on for NesCom and Standards Board approval.

Received on Mon Jun 28 12:27:18 2004