[vhdl-200x] Revision of path name proposal doc

Folks,

Here's round 2 of the path name doc. I've expanded the section dealing with
design hierarchy path names considerably, and made strawman proposals for
concrete path name syntax. I haven't proposed a strawman for a separate
character, since I think the issue of '.' vs ':' and Verilog
interoperability needs to be explored further. Also, I haven't had an
opportunity to look into the details of PSL to complete the sections
relating to it.

Nonetheless, comments invited...

Cheers,

PA

--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
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