Re: [vhdl-200x] Re: Requirements for Interfaces, Part 1

ftp://ftp.synopsys.com/pub/OpenVera_LRM_T_v2.3.pdf/OpenVera_LRM_T_v2.3.pdf

chapter 9 deals with how interfaces are done in OpenVera
the concepts here are more with how the language connects
to the HDL, but there might be some more ideas here of what to
include/not include in an interface. I had to register at the site
before it would let me have the LRM

so do we define an interface in VHDL to be a collection of
ports, signals, variables, enums? is it a standalone
thing? or required to go along with an existing VHDL
construct?

  -tim
Received on Thu Apr 22 11:31:55 2004