[vhdl-200x] Requirements for VHDL Interfaces

From: Jim Lewis <Jim@synthworks.com>
Date: Tue Apr 20 2004 - 11:53:08 PDT

Steve,
How is it comming with the requirements for interfaces?

If interfaces are to do sequences of signaling on
interfaces, then sequential code by itself is not
enough. Coding things like statemachines can be
more difficult without concurrent code (not undoable
just less flexible and at times, more complex).

In addition, it is nice to be able to bundle things
like protocol checkers and assertions with the interface
description.

These are some of the reasons why I transitioned from
using transaction based subprograms to using transaction
based BFMs in verification.

Cheers,
Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Received on Tue Apr 20 11:53:12 2004

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