[vhdl-200x] IP Protection in VHDL

All,
 
Cadence is putting together a donation to the 1076 WG that is based on the same donation that they have already made to 1364 for IP protection. While Cadence finishes dotting their i's and crossing their t's on the 1076 donation, Deepak has provided us with a link to the Verilog donation. That link is provided below.
 
I recommend that anyone interested in this area take some time to review the 1364 donation. It is expected that the 1076 donation will use the same fundamental encryption/decryption technology with only the syntactic sugaring/requirements of VHDL substituted for the same in Verilog.
 
Of course, I will let all know when the Cadence donation to the 1076 group is ready for review. Thanks to Cadence, Deepak and his colleagues for their contributions.
 
-Steve Bailey
 
-----Original Message-----
From: Deepak Pant [mailto:dpant@cadence.com]
Sent: Monday, April 12, 2004 4:38 AM
To: Bailey, Stephen
Cc: dpant@chanakya.cadence.com; Ajayharsh Varikat
Subject: Link to the 1364 IP Protection donation

Steve,

It is issue BTF issue # 358. Here is the link:

http://www.boyd.com/1364_btf/report/full_pr/358.html <http://www.boyd.com/1364_btf/report/full_pr/358.html>

rgds,

Deepak
Received on Mon Apr 12 07:36:58 2004