RE: [vhdl-200x] Issue with VHDL name attributes

Peter,

I sent another email earlier this morning, but I suspect that email didn't get out, because Outlook crashed just after I sent it - so I'll repeat myself here, just in case. Apologies if this is a duplicate.

I'm intrigued by the decision to make architectures a separate declarative region, nested 'inside' that of the entity. (I wasn't aware of this until this thread started.)

Architectures (or "architecture bodies", as they were originally refered to) are to entity (interface) declarations as package bodies are to package declarations. The only significant difference w.r.t. scope and visibility is that we wanted to allow alternative architectures, whereas one package body was deemed sufficient. The need to allow multiple architectures led to a requirement for names on the architectures.

If an architecture is now considered to be a nested declarative region inside an entity, then similarly a package body should be considered a nested declarative region inside a package declaration. If that is not the case, then the analogy between entity/architecture and package/package body has been broken. However, I see virtually no value in adopting this nested definition, in either case.

If the goal was to allow an architecture to have the same name as the corresponding entity, a much more natural solution would have been to simply make the architecture name optional:

entity E is ...
end;

architecture of E is ...
end;

There is only one name, and it is shared by the entity and the architecture - which together still constitute a single declarative region.

I wasn't involved in the discussions that led to the decision to change the definition of declarative regions, so I may be missing something. But on the surface, I don't see how it adds any real value, and it seems to tear a bit at the basic framework of the language.

Regards,

Erich
Received on Wed Apr 7 10:05:11 2004