Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g
From: Evan Lavelle (anti.spam1@dsl.pipex.com)
Date: Tue Dec 30 2003 - 04:06:55 PST
Erich Marschner wrote:
> In the context of PSL becoming a part of VHDL 200x, the first reason
> is perhaps irrelevant, and the situation upon which the second was
> predicated is no longer the case. It is therefore quite reasonable
> to reevaluate the question of what kind of expressions should be
> allowed as conditions in PSL directives that are part of VHDL 200x.
From my very cursory reading of the 1.01 LRM, it seems to me that there
may not actually be a real problem here, and VHDL200x can simply ignore
this issue. The LRM talks a lot about boolean conditions, but it defines
the value of a Boolean expression as:
> In a given flavor of PSL, the value of a Boolean HDL expression is interpreted as a logical value according to the
> same rules that govern interpretation of that expression as the condition of an if statement in that flavor.
This appears to be a Verilog-centric statement, and my guess is that
it's there to handle Verilog x and z. Could the problem be fixed simply
by changing this to:
"For the VHDL flavor of PSL, the value of an expression is interpreted
as a Boolean true if that expression evaluates to
STD.Standard.Boolean'(True), or that expression is of an enumerated type
and evaluates to the values '1' or 'H'. In all other cases, the
expression is interpreted as a Boolean false."
There seem to be some get-outs that might allow this: the PSL LRM states
that it overloads the logical operators, and HDL_EXPR seems to be
definable as a macro in some way. If this is possible, then we get
conciseness in PSL expressions without changing the base language at
all. Anyone who's using negative logic and is concerned that the PSL
expression looks like an incorrect boolean can simply expand out their
expression in the normal way.
You also quote the definitions of true and false in 3.1.20 and 3.1.52:
> - STD.Standard.Boolean'(False),
> - STD.Standard.Bit'('0'), and
> - IEEE.std_logic_1164.std_logic'('0')
> are all interpreted as the logical value False, and the values
> - STD.Standard.Boolean'(True),
> - STD.Standard.Bit'('1'), and
> - IEEE.std_logic_1164.std_logic'('1')
> are all interpreted as the logical value True.
Why is it necessary to leave out the metalogic values? This was
presumably because Verilog's x and z are neither true nor false, but the
'if' statement interpretation in the LRM makes 1 true, and 0,x,z false.
If this is the case, then presumably there's no need to ignore the VHDL
metalogic values, and they could also be defined as false? Does this
mean that 3.1.20 and 3.1.52 are incorrect for Verilog-flavor PSL?
On the separate issue of overloading +/- for conciseness, I have some
code which does this in C++: I overload unary plus to get a value out of
a complex class, to make it look like a simple built-in data type. It
seemed like a good idea at the time, but it's confusing to read and
leads to maintenance problems: it's only a matter of time before someone
removes a '+' on the grounds that unary + 'does nothing'.
Evan
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