Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g


Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g
From: Tim Davis (timdavis@aspenlogic.com)
Date: Tue Dec 23 2003 - 14:13:59 PST


[DISCLAIMER: I voted against this standard]

I **think** what you are saying Bhasker is that 1076.6 established that
the **synthesis** tool must accept the "type equivalence" of the
enumerated identifiers {'1', TRUE, 'H'} and {'0',FALSE,'L'}. The type
equivalence associations only work because the built-in VHDL operations
based on these types all have "active high" input/output
interpretations. There is no equivalent in VHDL to the schematic "OR"
symbol with bubbled inputs -- ie a DeMorgan equiv NAND gate.

However, they fail when you talk about assertion level. '1' is not
always asserted (active) true which I believe is Andy's point. While it
is ok for 1076.6 to be narrow minded because of its smaller domain of
applicability, I don't agree that it is ok for the VHDL language to be
narrow minded. Hardware is described in many ways and fixing the type
equivalence to the one above would be bad in my oppinion.

--
Aspen Logic, Inc.
By: Tim Davis, President

Jayaram Bhasker wrote:

>FYI. > >>From IEEE Std 1076.3-1997, IEEE Standard VHDL Synthesis Packages, Section 4 "Interpretation of logic values". > >4.3.1 "A synthesis tool shall interpret the following values as representing a logic value 0: >the BIT value '0', the BOOLEAN value FALSE, the STD_ULOGIC values '0' and 'L'. It shall interpret >the following values as representing a logic value 1: >the BIT value '1', the boolean value TRUE, the STD_ULOGIC value '1' and 'H'." > >Section 4.3.2 describes how metalogical values ('U', 'W', 'X', '-') are to be interpreted >in relational expressions, as a choice in a case stmt, in logical, arithmetic and shift operators, >in concatenate operations, in type conversion and sign-extension functions, and in assignments. > >Section 4.3.3 describes the interpretation of the high-impedance value 'Z'. > >- bhasker > >------ >J. Bhasker, eSilicon Corp >1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104 >jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax) > > > >-----Original Message----- >From: Bailey, Stephen [mailto:SBailey@model.com] >Sent: Friday, December 19, 2003 7:14 PM >To: 'vhdl-200x@eda.org' >Subject: RE: [vhdl-200x] Implicit conversion, Overloading, & Strong >Typin g > > >PSL defines boolean equivalence for std_ulogic. From the 1.01 version of the PSL LRM: > >"3.1.20 False: An interpretation of certain values of certain data types in an HDL. >In the Verilog flavor, the single bit value 1'b0 is interpreted as the logical value False. > >"In the VHDL flavor, the values STD.Standard.Boolean'(False), STD.Standard.Bit'('0'), and IEEE.std_logic_1164.std_logic'('0') are all interpreted as the logical value False. > >"In the GDL flavor, the Boolean value 'false' and bit value 0B are both interpreted as the logical value >False. > >"3.1.52 True: An interpretation of certain values of certain data types in an HDL. >In the Verilog flavor, the single bit value 1'b1 is interpreted as the logical value True. > >"In the VHDL flavor, the values STD.Standard.Boolean'(True), STD.Standard.Bit'('1'), and IEEE.std_logic_1164.std_logic'('1') are all interpreted as the logical value True. > >"In the GDL flavor, the Boolean value 'true' and bit value 1B are both interpreted as the logical value True. > >"5.1 HDL expressions > >A Boolean HDL expression, shown in Box 11 [this is the syntax productions], is any HDL expression that the HDL allows to be used as the condition of an if statement." > >NOTES: >1. I added some formatting (vertical white space) to increase readability. > >2. Ben Cohen has written in an earlier post that he has a proposal to modify the 1.1 LRM currently being written to include the meta-logic values of std_ulogic in the definition of false. > >3. For those who may not be aware: > > - Boolean expressions are the fundamental building block of sequences and properties (that is, they are prevalent throughout a PSL specification). > > - There are tools today (Safelogic, NC, ModelSim, others) that already support VHDL-flavor of PSL. > > - You can embed PSL inside the HDL and include arbitrary HDL within your PSL sections. (Again, the tools already support this.) > >PSL does not require COND as they have already defined a boolean equivalence. VHDL needs the COND proposal to be consistent with PSL and to improve language efficiency in expression (or whatever you wish to call "typing efficiency"). > >-Steve Bailey > > > >>-----Original Message----- >>From: owner-vhdl-200x@eda.org >>[mailto:owner-vhdl-200x@eda.org]On Behalf >>Of Hamish Moffatt >>Sent: Friday, December 19, 2003 4:30 PM >>To: 'vhdl-200x@eda.org' >>Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong >>Typin g >> >> >>Bailey, Stephen wrote: >> >> >>>- Do nothing to address an enhancement request that is elevated in >>>priority due to the desire to incorporate PSL as the property >>>specification capability in VHDL. (I already pointed out >>> >>> >>the obvious >> >> >>>language inconsistencies that arise if we do nothing.) >>> >>> >>Why is the COND operator required for PSL? >> >> >>Hamish >> >> >> > > >



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