RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003


Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003
From: Bailey, Stephen (SBailey@model.com)
Date: Fri Dec 19 2003 - 08:44:02 PST


Mark,
 
While it should not be possible for existing code to behave differently, the separate package for the predefined equivalence functions/operators is a reasonable idea. It helps to avoid accidental use of the capability with new designs or continued evolvement/maintenance of existing designs.
 
-Steve Bailey

-----Original Message-----
From: Mark Smallwood [mailto:Mark.Smallwood@alcatel.com]
Sent: Friday, December 19, 2003 4:27 AM
To: Bailey, Stephen; vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003

Steve,
 

And if vhdl-200x does define conditional equivalence for BIT, INTEGER etc. (as per your 11 december email ...
 

> With the new capability, it is further proposed that we exploit to define the OBVIOUS boolean equivalence of commonly used types:
> - BIT: 0 = FALSE, 1 = TRUE
> ...
 
) can we have the same option not to use it, please ? e.g. a package std.standard_conditional_equivalences.
 
In the applications where I use std.standard.bit this equivalence is absolutely not "OBVIOUS" (had it been so I would have used type boolean),
 
            mark.

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Bailey, Stephen
Sent: 18 December 2003 15:57
To: vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003

Hi Scott,
 
Your suggestion would be an option. Assuming the proposed context clause becomes part of VHDL, the impact of always using one more package is minimal.
 
I can't think of any other negative to the proposal. The obvious positive is that people that don't want it, shouldn't get it by accident.
 
-Steve Bailey

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org]On Behalf Of Scott Thibault
Sent: Thursday, December 18, 2003 8:45 AM
To: vhdl-200x@eda.org
Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,S an Jose Dec 4, 2003

Is there some reason that the equivalence operator needs to be defined in std_logic_1164? Would it be less objectionable if it were in another package like std_logic_bool or something like that? That way the user would need to explicitly request it.
 
--Scott Thibault
Green Mountain
Computing Systems, Inc.
http://www.gmvhdl.com <http://www.gmvhdl.com/>



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