[vhdl-200x] RE: Should we merge 1164 into 1076?

Subject: [vhdl-200x] RE: Should we merge 1164 into 1076?
From: Peter Ashenden (peter@ashenden.com.au)
Date: Wed Dec 17 2003 - 18:37:01 PST

John,

What the users chooses to use and what a comformant tool must implement are
different questions. Currently, a tool implementation must implement TEXTIO
to conform with the standard. We have no notion of optional parts - it's
all or nothing.

It would be possible to change that and specify conformace sets. Then, we
might add 1164 to 1076 and make std_logic_1164 an optional part for a tool
to implement.

Cheers,

PA 

--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
PO Box 640                                   Ph:  +61 8 8339 7532
Stirling, SA 5152                            Fax: +61 8 8339 2616
Australia                                    Mobile: +61 414 70 9106

> -----Original Message-----
> From: owner-vhdl-std-logic@eda.org 
> [mailto:owner-vhdl-std-logic@eda.org] On Behalf Of John 
> Michael Williams
> Sent: Thursday, 18 December 2003 13:04
> To: vhdl-std-logic@eda.org
> Cc: vhdl-200x@eda.org
> Subject: Re: Should we merge 1164 into 1076?
> 
> 
> Hi Peter.
> 
> If we included the 1164 package in 1976 as
> an annex for convenience of users, with some
> explanations, the maintenance
> would be simplified, but there still would
> be the choice of not using 1164.
> 
> For example, there is no requirement to use
> TEXTIO.
> 
> I don't see the stopping criterion as a problem,
> unless someone sees good reason to start up
> annexation again . . ..
> 
> -- 
>                           John
>                       jwill@AstraGate.net
>                       John Michael Williams
> 
> Peter Ashenden wrote:
> > Dear colleagues,
> > 
> > [Disclaimer: I am speaking here as a WG member, not as DASC Chair.]
> > 
> >>From time to time, it has been suggested that we merge the standard 
> >>logic
> > package definitions into the base VHDL standard document.  I would 
> > like to see if there is currently interest in doing so.
> > 
> > The reasons for doing so are:
> > 
> > (1) The standard logic types are so widely used in VHDL 
> modeling now 
> > that they have become an integral part of the language and its 
> > environment.
> > 
> > (2) Maintaining the standards separately is an administrative and 
> > logistical burden.  In particular, ensuring that revisions are 
> > synchronized is difficult.  Since most of the people 
> involved in P1164 
> > are also actively involved in P1076, they could work as a 
> functional 
> > team of P1076 with less overhead.
> > 
> > Reasons agains are:
> > 
> > (3) Adding the standard logic types to P1076 would mean all 
> VHDL tools 
> > would have to provide them, whereas now, a tool vendor could decide 
> > not to implement them and still be compliant with 1076.
> > 
> > (4) If you merge 1164 into 1076, do you then do 1076.2?  
> And 1076.3? 
> > 1076.4? Where does it stop?
> > 
> > Comments?
> > 
> > Cheers,
> > 
> > PA
> > 
> > --
> > Dr. Peter J. Ashenden                        peter@ashenden.com.au
> > Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
> > PO Box 640                                   Ph:  +61 8 8339 7532
> > Stirling, SA 5152                            Fax: +61 8 8339 2616
> > Australia                                    Mobile: +61 414 70 9106
> > 
>

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