Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: Rick Munden (munden@acuson.com)
Date: Wed Dec 17 2003 - 09:01:22 PST
Sorry everyone but I agree with Andy.
Rick Munden
Andy D Jones wrote:
> Well said! We need more functionality, not shortcuts!
>
> Am I the only one that is concerned with defining '1' in std_logic to be
> TRUE? (and conversely, '0' to be FALSE)? VHDL is supposed to be
> technology independent! Its application extends far beyond the IC, to
> boards where active low signals are still preferred. This definition
> would make vhdl unusable at other than the IC and FPGA level.
>
> The point is, 1164 was created to allow more accurate modelling of
> actual hardware signal levels, etc., not to enhance behavioral (which
> most of RTL has become) semantics. It explicitly divorces signal levels
> from boolean interpretations for just that reason. If a circuit needs
> to do something in response to a high level on a signal, then it should
> be so stated. It should not be confused with whether a boolean condition
> indicated by that signal level is TRUE (whatever TRUE means).
>
> Numeric_std.unsigned was kept separate from std_logic_vector for the
> same reason. An implied conversion from vector to number space is
> ambiguous, the same way an implied coversion from signal level to
> boolean is ambigous. And VHDL is all about avoiding ambiguity!!!
>
> The example given about unsigned addition adds nothing to the argument.
> The mear usage of an unsigned data type gives explicitness to the
> definition of the operation to be performed. In the Unsigned data type,
> a '1' means a given power of two if set to one. This is part and parcel
> of the definition of unsigned.
>
> If we allow implied conversions of std_logic to boolean in conditionals
> today, what will the whining masses want us to allow next? And then
> they will have precedence for getting their way!
>
> What happens when someone writes "elsif clk then..."? Do we assume that
> he wants the rising edge? What if he writes "elsif not clk then..."?
> Do we assume it is not a clock event, or that he wants the falling
> edge? This is exactly what I've been talking about: where will
> designers want to use this that is completely ambiguous and confusing?
>
> I say we keep std_logic at the signal level, and not have an implicit
> conversion to boolean under any circumstances. If you want to be able
> to avoid conversions in conditional expressions, use boolean data types
> in the first place, and leave std_logic as it is!
>
> Andy Jones
> Lockheed Martin
> Missiles & Fire Control
> Dallas TX
>
>
> Munden Rick wrote:
>
> (snip...)
>
>> Sometimes it is appropriate to build in stucco and other times in
>> stone. We don't need to merge VHDL and Verilog to come out with
>> something in the middle. Each language has its place. I would rather
>> see us concentrate on adding actual capability than just adding
>> shortcuts.
>>
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