Subject: Re: [vhdl-200x] To_Boolean(std_obj) vs if std_obj
From: Andy D Jones (firstname.lastname@example.org)
Date: Wed Dec 10 2003 - 13:52:20 PST
I'll go along with whatever the community wants. However, it is thisvery "strong" typing issue that can get carried away, and frustrates many engineers,who find "relief" when transitioning to Verilog. I am not saying that Verilog is better than VHDL - so no war here. However, I see no harm in interpreting std_ulogic in an "if" statement as a Boolean. The way that would work would be an "implicit" call to a "to_Boolean" function defined in an IEEE package. That function is called with the "if std_uLogic_object then ". In that case, there is no ambiguity as to what is meant by the implicit conversion.PSL users and LRM authors decided to make that interpretation.I am a strong proponent of making code more readable. The "if to_boolean(some_signal) then" is less readable than "if (some_signal) then". For the skeptical on this, see Verilog code, and talk to Verilog users.Note: Adding the implicit to_boolean type conversion in an "if std_ulogic_object" does not violate the string typing of VHDL.Bensnip...
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