Re: [vhdl-200x] To_Boolean(std_obj) vs if std_obj

Subject: Re: [vhdl-200x] To_Boolean(std_obj) vs if std_obj
From: Andy D Jones (andy.d.jones@lmco.com)
Date: Wed Dec 10 2003 - 13:52:20 PST

I really don't like "to_boolean(std_logic)", and especially not implicit calls to it.  What is 'true' in std_logic?  What if the argument is "enable_n"  (active_low)? What about weak values? What about metavalues?  What do we do if the condition is an expression like "my_sl and my_boolean"?  Do we allow that as well?  Then what?  And how much more difficult will it be to teach users all these things? This slope is gettin' mighty slippery! I vastly prefer something that says what value it is, such as is1() or is0(), and explicitly calling it.

If we define a standard function "to_boolean()" that assumes '1' is true, then that is the same as making "if my_std_logic then" work, which completely defeats the purpose of strong typing.  As soon as we do it for std_logic, then we're gonna have to do it for integer, slv, signed, unsigned, etc.  It won't end until there is no data typing left.

I know there are a lot of people that don't like strong typing.  Tell them to use verilog.  Don't take away the feature that defines what most of us believe is vhdl's strongest attribute, just to entice users that would rather use a different language anyway.

If you want the most readable, concise, yet explicit code, use boolean values in the first place. 

If you want readable, somewhat concise code, use is1() or is0() (or equivalents that indicate what bit level is 'true').

But don't weaken vhdl's strong data typing.

Andy D Jones
Lockheed Martin
Missiles & Fire Control
Dallas TX
andy.d.jones@lmco.com

VhdlCohen@aol.com wrote:
I'll go along with whatever the community wants.  However, it is this
very "strong" typing issue that can get carried away, and frustrates many engineers,
who find "relief" when transitioning to Verilog.  I am not saying that Verilog is better than VHDL - so no war here.  However, I see no harm in interpreting std_ulogic in an "if" statement as a Boolean.  The way that would work would be an "implicit" call to a "to_Boolean" function defined in an IEEE package.  That function is called with the "if std_uLogic_object then ".  In that case, there is no ambiguity as to what is meant by the implicit conversion.  
PSL users and LRM authors decided to make that interpretation. 
I am a strong proponent of making code more readable.  The "if to_boolean(some_signal) then" is less readable than "if (some_signal) then".  For the skeptical on this, see Verilog code, and talk to Verilog users.    
 
Note: Adding the implicit to_boolean type conversion in an "if std_ulogic_object" does not violate the string typing of VHDL. 
Ben
 
snip...

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