Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec...
From: Jim Lewis (Jim@synthworks.com)
Date: Tue Dec 09 2003 - 19:39:46 PST
VhdlCohen@aol.com wrote:
> In a message dated 12/9/2003 5:52:53 PM Pacific Standard Time,
> Jim@synthworks.com writes:
>
> - Boolean Equivalence
> >
> > Please don't. Implicitly assuming a boolean value leads to
> > confusion. We should not trade the type-safe nature of VHDL for
> > (debatable) convenience. Is it really so much better to type "if
> > (<signal>)", than "if (<signal> = '1')"? How about the less-obvious
> > case "if (resetn)"? Should that read as "resetn = '1'" or
> "resetn is
> > active (low)". VHDL would have to assume the former, while users
> > browsing the sources would be tempted reading the latter statement
> > into the code.
>
> Currently it is needed/desired in the PSL context.
> We are evaluating whether it makes sense in a wider context.
> I am kind of leaning in the same direction you are.
> Other members of the group are pushing in this direction.
> To me it has not hit my
>
> Actually, current PSL already interprets STD_uLogic '1' and '0' as
> Boolean true / false.
>
Agreed.
So the purpose of the boolean equivalence slide is to make
this legal within any conditional expression in VHDL (and not
just in PSL). It has some interesting issues.
Cheers,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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