Re: [vhdl-200x] Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003


Subject: Re: [vhdl-200x] Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: VhdlCohen@aol.com
Date: Tue Dec 09 2003 - 09:37:13 PST


Good comments, and I am also in agreement.
Thus, use of "when" in concurrent assignment statements,
and "if" in sequential assignment while maintaining the form
  in a process:
    S <= Q if condition else
            W if other_condition else
            K;
In a process, I would also support the variables to have that sturcture, thus:
   V := Q if condition else
            W if other_condition else
            K;
Ben Cohen

In a message dated 12/9/2003 9:13:34 AM Pacific Standard Time,
andrew_guyler@mentorg.com writes:
I have to agree with Andy...

"I would definitely NOT deprecate the use of "when" in conditional signal
assignments, since deprecation is usually applied only to seldomly used language
features, which is certainly not the situation here. For deprecation to have
any meaning, it would eventually lead to removal from the standard, which would
break untold thousands of lines of legacy code."
  
    Andrew Guyler
    Mentor Graphics

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org]On Behalf Of
Andy D Jones
Sent: Tuesday, December 09, 2003 6:50 AM
To: VhdlCohen@aol.com
Cc: Jim@synthworks.com; vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Minutes for VHDL-200X-FT meeting, San Jose Dec 4,
2003

[I subscribe to this list, but have not been able to post to it in the past,
so if it this does not make it onto the list, if one of you kind Gentlemen
would forward it, I'd appreciate it.]

WRT adding "if else" to conditional signal assignments, and possibly
deprecating "when else":

I prefer the use of "when" in concurrent assignment statements, since it
confers the context of the assignment as "whenever". Whereas "if" confers an
immediate condition that must exist at a certain time. The actual enforcement of
these meanings is performed by the (virtual) processes surrounding each, but
they remain a helpful reminder to the reader.

If conditional assignments were allowed in sequential assignment statements
(which I do support), I would prefer that they use "if" in those cases, to
preserve the "whenever" nature of "when" in concurrent assignments. I realize that
"when" is also used in sequential case statements without meaning "whenever",
but that's a legacy of Ada and other lanquages that do not have a concurrent
statement context.

The use of "when" in concurrent conditional signal assignments is a commonly
used feature, and changing it now would be very confusing to the majority of
users. While I agree that the use of "when" is often confused with selected
signal assignments, this has been the case for too long to change now. It has
become "just one of those things you have to know" about VHDL.

I would definitely NOT deprecate the use of "when" in conditional signal
assignments, since deprecation is usually applied only to seldomly used language
features, which is certainly not the situation here. For deprecation to have
any meaning, it would eventually lead to removal from the standard, which would
break untold thousands of lines of legacy code.

Furthermore, in the absence of deprecating the use of "when" in conditional
assignment statements, I cannot support the addition of "one more way" to code
the same thing that is not substantially more efficient, and does not confer
substantially different context.

Andy D Jones
Lockheed Martin
Missiles & Fire Control
Dallas TX
andy.d.jones@lmco.com

VhdlCohen@aol.com wrote:

snip...

--------------------------------------------------
Add "if else" for conditional signal (deprecate when else?)
AReg



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