Subject: RE: [vhdl-200x] RE: Advisory vote: simple subset of PSL
From: Tom Fitzpatrick (Tom.Fitzpatrick@synopsys.com)
Date: Fri Sep 12 2003 - 10:59:40 PDT
Hi Stephen,
Thanks for your response, and for adding me to the reflector.
I appreciate the difference between "cut-and-pasting" the PSL LRM and
incorporating it by reference. As you point out, PSL1.01 is an Accellera
standard and can be used in this context, I believe. Since Accellera has
decided to move PSL to 1.1 to be compatible with SystemVerilog, and will, I
imagine, encourage vendors and users to move along with them, I encourage
VHDL-200x to be flexible on this point. I'd also encourage you to remind
your audience of this fact whenever appropriate.
As a representative of a vendor, I think there is a lot of value in reducing
the number of languages that need to be supported. If we can agree on a
"reduced subset" of assertion capability that is consistent between
VHDL-200x and SystemVerilog/Verilog-200x, then everyone will benefit. I
believe that the VHDL-200x committee is actually in a better position than
the FVTC in that you can actually define the proper scheduling semantics for
assertions in VHDL, such that any given assertion expression will get a
consistent answer between VHDL and Verilog, for both simulation and formal
verification.
Thanks for your reply,
-Tom
> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org]On Behalf
> Of Bailey, Stephen
> Sent: Friday, September 12, 2003 1:45 PM
> To: 'Tom Fitzpatrick'
> Cc: vhdl-200x@eda.org
> Subject: [vhdl-200x] RE: Advisory vote: simple subset of PSL
>
>
> Hi Tom,
>
> > As a DASC member, I'd like to vote in opposition to your proposal:
> >
> > > > Should the assertions team continue constructing a
> > detailed language
> > > > change proposal based on incorporating and integrating
> > PSL into VHDL?
> > > >
> >
> > It is premature for the VHDL-200x committee to consider
> > incorporating PSL in
> > VHDL for two simple reasons. The first is that the Accellera Board of
> > Directors has not donated PSL to the IEEE for consideration. Further,
> > Accellera plans to change PSL in PSL1.1 to be compatible with
> > SystemVerilog.
>
> Neither of these are a problem on the face of it given that this
> is an advisory vote and we still have quite a bit of work to do
> before a complete technical proposal is ready. Additional
> responses are included below.
>
> First, neither the WG nor the IEEE requires that PSL be an IEEE
> standard. The 1.01 version of PSL was approved by the Accellera
> board as reported in the 2 June 2003 Press Release
> http://www.accellera.org/press19.html.
>
> Second, we have no plan or desire to duplicate or modify the PSL
> standard by physically incorporating it (duplicating in part or
> whole) into the VHDL standard. It will be incorporated by
> reference. Therefore, any Accellera (or IEEE, if PSL has been
> donated to IEEE by then) changes to PSL up to a cut-off point
> determined by when we (the WG) decide it is OK to ballot will be
> automatically included. This is entirely in compliance to
> Accellera's "Declaration of Conditions of Use Without License
> Accellera Property Specification Language"
> http://www.accellera.org/pslconditions.html.
>
> Third, the WG does not have any desire to incorporate a standard
> that is obsolete. Therefore, I would expect the WG to make the
> decision on when it can go to ballot to be consistent with a
> suitably stable version of PSL. (Since the Accellera board
> approved 1.01, it must have a reasonable level of stability.)
>
> > Therefore, if the VHDL-200x committee wishes to get a
> > head-start on a simple
> > subset of assertions, they should consider SystemVerilog
> > assertions. The
> > VHDL-200x committee investigation of PSL1.01, which will
> > change, is not a
> > prudent use of resources.
> >
> > If you or other committee members wish to publish articles or
> > conference
> > papers about ABV in VHDL, these papers should accurately reflect the
> > situation, not promote the further perpetuation of "language wars."
>
> The articles do not perpetuate any language wars. The only
> language war currently in progress is the battle between
> SystemVerilog and 1364-2005. This WG has no opinion and takes no
> sides in that particular war and the articles make no mention of
> either SystemVerilog or Verilog 1364 (any version). This WG only
> wishes to incorporate ABV capabilities into VHDL in a manner that
> provides good value to VHDL users while being expeditious and
> likely to be implemented by EDA vendors. Therefore, to the
> extent that PSL and SystemVerilog Assertions evolve to be more
> compatible with each other, that would only serve to further our
> objectives.
>
> I would like to thank you for pointing out that changes to the
> PSL LRM are planned. We will communicate with the Accellera FVTC
> and follow their progress and plans to ensure we do not send the
> VHDL ballot prematurely.
>
> BTW: You were not subscribed to vhdl-200x so your email bounced.
> I have subscribed you to the list. For the benefit of the rest
> of the list, I have attached Tom's original email.
>
> ------------
> Stephen Bailey
> TME, Mentor Graphic's Model Technology Group
> sbailey@model.com
> 303-775-1655 (mobile, preferred)
> 720-494-1202 (office)
> www.model.com
>
>
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