Subject: Re: [vhdl-200x] Simple Subset of PSL: Strong Affirmative Vote
From: John Willis (john.willis@ftlsys.com)
Date: Wed Sep 10 2003 - 13:10:37 PDT
Steve,
I am voting strongly in favour of the motion.
We have been working with PSL directly and with extensions for
mixed signal and asynchonrous design. I believe it provides a
solid and well-conceived foundation that could only be replaced
by several years of intense effort. Such replacement is not
likely to be funded and would not serve any useful purpose in
my opinion. Hence the response to your motion is a strong
affirmative.
As a meta-point not directly applicable to the motion, I am
concerned about limiting use of PSL to "simulatable usage".
There is also a concern that PSL is most effective when set
off in a distinct block, perhaps an assertion block, rather
than attempting to merge directly into the more general VHDL
syntax. Glad to defend both points in an appropriate forum.
Best regards, John
--On Wednesday, September 10, 2003 12:48:22 PM -0700 "Bailey, Stephen"
<SBailey@model.com> wrote:
> The assertions team has decided to pursue the incorporation and
> integration of the simple subset of PSL as the best way to enhance the
> assert statement into a broader assertion-based verification capability.
> The simple subset limits the properties that can be expressed to only
> those in which time moves monotonically forward (which is the only way
> simulators know how to deal with time).
>
> Because we do not yet have a detailed proposal on the specifics of the
> PSL incorporation and integration, this Call for Vote is NOT a final CfV.
> Instead, it is best viewed as an advisory vote; the purpose of which is
> to provide some assurance to the assertions team that they won't be
> wasting their time in pursuing PSL as the basis for the detailed
> proposal. (By assurance, I mean that we won't later find out that a
> majority or very significant minority would never vote to approve the
> detailed proposal due solely to the fact that the proposal is based on
> PSL.)
>
> Also, from a practical perspective, I am in the process of submitting 3
> different papers for possible publication and presentation at conferences
> and EE Times. These papers will all reference the fact that PSL has been
> chosen as the basis for VHDL's ABV capabilities. While I don't
> anticipate a negative response to this advisory vote, I would rather have
> the vote than be made a fool (and waste alot of people's time over the
> next several months)!
>
> As the papers are in process of review and this is an advisory vote, I
> require a quick turnaround on this vote:
>
> Friday, 12 Sep 03, 0900 EDT.
>
> The question to be voted on:
>
> Should the assertions team continue constructing a detailed language
> change proposal based on incorporating and integrating PSL into VHDL?
>
> Yes replies require no comments. However, I request any no responses to
> provide rationale for the no comment. Replies can be sent to me
> (mailto:sbailey@model.com) or to the email reflector
> (mailto:vhdl-200x@eda.org).
>
> DASC WG voting rules apply. You must be a DASC member. To confirm your
> membership in DASC, see http://www.dasc.org/DASC-roster.html. The DASC
> home page has a link to the membership application.
>
> Thank you for your prompt consideration.
>
> ------------
> Stephen Bailey
> TME, Mentor Graphic's Model Technology Group
> sbailey@model.com
> 303-775-1655 (mobile, preferred)
> 720-494-1202 (office)
> www.model.com
>
-----------------------------------------------------------
John Willis jwillis@ftlsys.com
FTL Systems Inc. FTL Systems UK Ltd
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