Subject: Re: [vhdl-200x] Language bloat
From: Farrell Ostler (Farrell.Ostler@xilinx.com)
Date: Mon Jul 21 2003 - 09:04:09 PDT
I share Scott's concern about the large list of potential language enhancements.
VHDL seems to be a daunting language to implement completely and
correctly. How much are we willing to exacerbate this aspect?
Farrell Ostler
Scott Thibault wrote:
> Hello everyone,
>
> There seems to be a substantial list of features that are being considered
> for inclusion in the next VHDL, and I wonder if it would not be a good idea
> to check ourselves on this issue of language bloat. I've spent a good
> amount of time studying domain-specific languages, and would like to share
> some of my thoughts about this issue. I think they apply to our work as a
> whole but specifically there are a number of things in the TBV group that
> should be considered, such as fifos.
>
> The primary distinction between a general-purpose language and a
> domain-specific language, is that general-purpose languages strive to
> provide powerful abstraction mechanisms (e.g., the ability to create classes
> or functions), where as a domain-specific language attempts to provide the
> right set of predefined abstractions for a given domain (e.g., built-in
> primitives/types specific to the domain). I consider VHDL to be kind of in
> between, what I call a domain-oriented language. It is general purpose in
> the sense that you can write virtually any program in VHDL (i.e. the design
> space is huge), but yet it has domain specific features that make it
> particularly useful for a certain domain of applications (i.e. event-driven
> simulation, which is still a large domain). Our current effort will push
> VHDL even more towards the general purpose of the spectrum by trying to
> enlarge the design space to include testbench and system level design.
>
> Because VHDL tries to address multiple and large domains, I think it would
> be unwise to attempt to provide predefined abstractions that will be
> necessary for those domains, but rather focus on providing the powerful
> abstraction mechanisms that will enable us to create the VHDL packages
> needed for the various domains we are trying to address. For example,
> rather than adding a predefined notion of a fifo in VHDL, why not provide
> some kind of parameterized types that would allow us to build a verification
> package that would allow users a convenient way to create fifos?
>
> VHDL is already a large language, so these are some things to think about.
>
> Regards,
> --Scott Thibault
> Green Mountain
> Computing Systems, Inc.
> http://www.gmvhdl.com
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