Re: Subject: RE: [vhdl-200x] [Fwd: Multi-dimensional arrays in components usi...


Subject: Re: Subject: RE: [vhdl-200x] [Fwd: Multi-dimensional arrays in components usi...
From: VhdlCohen@aol.com
Date: Mon Jul 14 2003 - 13:03:39 PDT


In a message dated 7/14/2003 9:37:43 AM Pacific Standard Time,
stephen@srbailey.com writes:
> In summary I am in favour of Proposal 2, Form 1. Plus the
> definition of:
>
> type std_logic_mem is array ( natural range <> ) of std_logic_vector ;
> in the 1164 package.
>

I second that proposal. We'll have to discuss in the LRM the implicit
operations as a result of the type definition (i.e., the relational operators). I
don;t envision an issue there.
Ben

----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
   Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------



This archive was generated by hypermail 2b28 : Mon Jul 14 2003 - 13:06:32 PDT