Subject: Re: [vhdl-200x] RE:
From: Wolfgang Roethig (wroethig@necelam.com)
Date: Mon Jun 09 2003 - 14:31:40 PDT
Hello John,
Please note that my assessment was not meant
to convey any personal opinion.
I wrote:
> People have argued that VHDL has already
> a richer description capability than Verilog,
> and SystemVerilog basically catches up with VHDL.
You wrote:
> By the way, it is unfair to characterize SV as merely catching up to VHDL.
> SV brings some important new modelling and verification features to the
> language.
I don't want to start a discussion about which language is more
complete. As I wrote, other people have started that discussion.
To a certain degree, I am a supporter of "competing" standards,
as long as the competition is healthy, stimulates advancement
(such as important new modelling and verification features) and
leads to a better end result.
Wolfgang
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> From: "John Shields" <jshields@synopsys.com>
> To: "Paul J. Menchini" <mench@mench.com>, <vhdl-200x@eda.org>
> Subject: [vhdl-200x] RE:
> Date: Mon, 9 Jun 2003 14:08:17 -0700
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> Wolfgang,
>
> I agree with the general philosophy of understanding what SV has done
> and to consider interoperability in judging the worthiness of new
> features for VHDL. I also agree with the priority you cite. In this
> particular area, noting what V95 is and
> SV adds, it is important to abstract the requirements and bring
> into VDHL a clean result that covers them.
>
> I agree with Kevin and Peter. A declarative model for a dynamic process
> and an instantiation construct is a better direction. Fork/join was
> a limited idea and the extensions made to it in SV extended the
functionality
> in as clean a way as the existing language allowed. VHDL can do better.
>
> By the way, it is unfair to characterize SV as merely catching up to VHDL.
> SV brings some important new modelling and verification features to the
> language. VHDL has an opportunity to achieve a similar functional result
> with cleaner semantics. VHDL 200x can also fall victim to being overly
> ambitious such that delivering results can not be afforded in a timely
> manner.
>
> Regards,
> John
>
> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org]On Behalf
> Of Paul J. Menchini
> Sent: Monday, June 09, 2003 10:11 AM
> To: vhdl-200x@eda.org
> Subject:
>
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> From: Wolfgang Roethig <wroethig@necelam.com>
> Reply-To: Wolfgang Roethig <wroethig@necelam.com>
> Subject: Re: [vhdl-200x] Re: Fork/Join
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>
> "Fork" and "join" is actually Verilog 95.
> Statements enclosed by "fork" and "join" are
> executed concurrently, whereas statements
> enclosed by "begin" and "end" are executed
> sequentially.
>
> Since translators and simulators with dual
> language support have been around for a while,
> the VHDL equivalent of "fork" and "join" should
> already exist. No need to extend VHDL for this
> feature.
>
> People have argued that VHDL has already
> a richer description capability than Verilog,
> and SystemVerilog basically catches up with VHDL.
>
> Therefore my recommendation is to establish a
> correspondence between VHDL and SystemVerilog first
> before creating a list of required VHDL enhancements.
>
> Wolfgang
>
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> > To: vhdl-200x@eda.org
> > Subject: [vhdl-200x] Re: Fork/Join
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> >
> >
> > I noticed that adding fork/join (a la SystemVerilog) was on
> > someone's list of enhancements. I would highly recommend not
> > adding fork/join and instead just add a means of creating
> > single threads dynamically and add proper thread control
> > in the style of the Posix threads library - the fork/join
> > syntax doesn't lend itself to capturing thread identifiers
> > and makes fine-grained control difficult.
> >
> > Kev.
> >
>
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