Subject: Re: [vhdl-200x] Re: [vhdl-200x-dta] Object oriented VHDL
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue May 20 2003 - 10:27:49 PDT
> From: "Mark Zwolinski" <mz@ecs.soton.ac.uk>
>
> Dear All,
>
> The other aspect that is related to this and has become moribund is the
> work on interface design and channels. The working group notes are still
> on-line at http://www.eda-twiki.org/sid/ . There was a product - VHDL+ - that
> implemented some of these ideas, although it didn't quite look like
> "real" VHDL.
>
> The team working on VHDL+ went to a spin-out company
> http://www.spiratech.com/ (I hope they don't mind the publicity!).
>
> Mark Zwolinski
I tried adding "channels" to SystemVerilog 3.0, but it got shelved for 3.1
and then Vera got donated which has them - but they are called "mailboxes"
(remember VMS?). Although they are called mailboxes they behave like
channels, the only problem is that a lot of the Vera stuff was originally
implemented through PLI so everything is allocated dynamically rather
than statically which was unfortunately carried through to SystemVerilog
and makes for some whacky syntax and semantics!
If anyone wants to write up a proposal for channels I would like to see
something where a channel is fairly interchangable with a signal, i.e.
most code that accesses a signal would be polymorhic and could access
a channel instead just by changing the signal type.
Note: some of my original motivation was due to testbenches at National
using a "backplane" to C++, and I wanted to use channels as a language-
neutral communication mechanism (an HDL channel would be mapped to a
C/Unix pipe file descriptor).
Kev.
> Paul J. Menchini wrote:
> > Hamish and all,
> >
> >
> >>>>I was wondering if anyone has been looking at a more object-oriented
> >>>>type system for VHDL - since the competion for simulating systems
> >>>>seems to be C++ (SystemC) and SystemVerilog, and they both have that.
> >>>
> >
> >>>There was a great deal of work a few years ago. See
> >>>http://eda.org/oovhdl. I don't think this completely up to date, but
> >>>it does contain the two proposals that were ultimately voted upon.
> >>
> >
> >>There's some detailed SUAVE information here:
> >>http://www.ashenden.com.au/suave.html
> >
> >
> > Thanks--I'd forgotten about that site.
> >
> >
> >>This proposal looks very good. I think it makes sense to use the
> >>Ada'95 concepts and syntax. I could start using some of these features
> >>immediately, if they were available. Unfortunately it looks like it
> >>lost out to Objective VHDL, which isn't going anywhere either.
> >
> >
> > Well, as the group is dormant, I don't see that this group has to abide
> > by their decision to go forward with Objective VHDL. We can revisit the
> > whole thing, if we desire.
> >
> > Paul
>
>
> --
> ===================================================================
> Dr Mark Zwolinski
> Electronic System Design Group Tel. (+44) (0)23 8059 3528
> Electronics & Computer Science Fax. (+44) (0)23 8059 2901
> University of Southampton Email. mz@ecs.soton.ac.uk
> Southampton SO17 1BJ, UK http://www.ecs.soton.ac.uk/~mz
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