Subject: Re: [vhdl-200x] New parameter mechanism wanted
From: Steve Casselman (sc@vcc.com)
Date: Fri Mar 21 2003 - 09:51:20 PST
This makes me think of Java reflection. I'm not sure how the code would look
that you are suggesting but maybe
comp1: comp port map (.....);
myparam = comp1'getparm(gate_timing);
So instead of just passing something up you would have to call it
explicitly.
Steve
http://java.sun.com/j2se/1.3/docs/api/java/lang/reflect/package-summary.html
----- Original Message -----
From: "Jay Lawrence" <lawrence@cadence.com>
To: "Jonas Nilsson" <jonas@hardi.se>; "Paul J. Menchini" <mench@mench.com>
Cc: <vhdl-200x@server.eda.org>
Sent: Friday, March 21, 2003 7:08 AM
Subject: RE: [vhdl-200x] Transmission gate mechanism and new parameter
mechanism wanted
>
>
> Verilog allows this capability via the 'defparam' statement. A defparam
> can be used to set a parameter value anywhere in the hierarchy
> (including your own parent) and there is no end to the pain and
> frustration it causes implementors.
>
> User's do end up creating loops between parameter values. Because of
> historical precedence for this we build a dependancy graph and only
> allow one iteration through the loop and then just stop. In the Verilog
> 2001 world some restrictions on generate statements in Verilog were
> added to not make the problem even worse but it still exists for regular
> instances.
>
>
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