Subject: RE: [vhdl-200x] Transmission gate mechanism and new parameter mechanism wanted
From: vhdl-200x@grfx.com
Date: Fri Mar 21 2003 - 01:30:48 PST
> From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
>
> > From: vhdl-200x@grfx.com [mailto:vhdl-200x@grfx.com]
> > Subject: Re: [vhdl-200x] Transmission gate mechanism
> > > 1) Transmission gate
> > It's not so much ports but how driver resolution is performed
> > that needs
> > to be different if you want to do bi-directional signal flow
> > - it needs
> > to be flat rather than hierarchical - you also need to add
> > functionality
> > (maybe as implicit signals) to let a process interrogate the
> > drivers of
> > a net so that it can differentiate it's own driver from
> > others. (That's
> > if you want to do it as abstract functionality rather than
> > add primitives.)
>
> I have in the past suggested (informally, on comp.lang.vhdl)
> that a new signal-valued signal attribute 'OTHER_DRIVERS
> could be added, whose value would be the resolved value
> of all drivers on the signal EXCEPT the driver in the
> current process context. I believe this would solve
> the great majority of "transmission gate" problems without
> the need for new primitives.
>
> Is this completely wrong-headed? Have I missed something
> important and obvious?
> --
> Jonathan Bromley, Consultant
You're right, that should work. We added some of this functionality
in Verilog-AMS for handling D->A conversion - other functionality
that is useful in an AMS context is being able to interrogate the
scheduled events on each driver. Rather than 'other_drivers we
treated the drivers as an array and let the process know the index
of it's own driver, and the indices of drivers that have changed.
I think it should be syntactically cleaner to do it in VHDL with
implicit signals.
Regards,
Kev.
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