Subject: Re: [vhdl-200x], vital issues
From: Steve Casselman (sc@vcc.com)
Date: Fri Mar 14 2003 - 08:53:11 PST
Well here is what I was thinking. Correct me if I'm wrong. Every tools that
puts out a Verilog gate level netlist also puts out EDIF. There are other
tools and languages that put out EDIF like schematic capture and SystemC.
Also any new language or high level entry system will export EDIF. I'm
pretty sure EDIF can describe anything that can be described in _gate_
level Verilog. But I'm sure your points are valid.
The real question is did Vital hamstring VHDL simulation speed to the point
were engineers _have_ to use Verilog to get their work done in a timely
fashion? If that is the case then why not have a "gate level VHDL" format?
Of course this would be structural VHDL linked against a simple non-Vital
library that can be simulated as fast or faster than gate level Verilog. Let
vendors output someone's Verilog work in "gate level VHDL." This way every
other entry system would be able to get the same benifits. We could call it
SuperSpeed VHDL or some such thing.
Steve
----- Original Message -----
From: "Stephen Bailey" <Stephen.Bailey@synopsys.com>
To: "Steve Casselman" <sc@vcc.com>; "Ray Andraka, Andraka Consulting Group,
Inc" <ray@andraka.com>
Cc: <vhdl-200x@server.eda.org>
Sent: Thursday, March 13, 2003 6:03 PM
Subject: Re: [vhdl-200x], vital issues
> No one has yet stated the obvious, so I will. EDIF is not a modeling
language. It is a netlist (connectivity) language. There is
> no way to describe behavior/functionality in EDIF. Any behavior
associated with the primitives in an EDIF netlist are provided at
> the discretion of some tool or that tool also has access to some other
library that the EDIF netlist is implicitly or explicitly
> referencing. The library would then contain behavioral/functional
information. Therefore, defining an interface to EDIF is
> incomplete, at best, as EDIF is missing the functional aspect required for
simulation.
>
> The other obvious point is that the number of people doing mixed VHDL/EDIF
simulations is trivial compared to the number doing mixed
> VHDL/Verilog simulations. Therefore, market demands indicate that
VHDL/Verilog has higher priority.
>
> -Steve Bailey
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