RE: [sv-sc] RE: [sv-champions] Mantis 1728 - let

Hmm,


	--- 6 ---

	There are two module declarations that begin

	 

	    module m(input bit clock);

	 

	But there are, unfortunately, still no 2-state wires in
SystemVerilog, so these should be

	 

	    module m(input var bit clock);

	 

	[SB] or 'input logic clock' or simply 'input clock', since there
does not seem to be any need in the examples for clock to be 2-state.

	 

	Also, example (f) has 

	 

	module m(logic clock);

	 

	While not incorrect, this declares clock as inout, which was
probably not the intent.

	 

	More seriously, both examples (e) and (f) refer to both "clock"
and "clk". It needs to be consistent.

	 

	--- 7 ---

	"let_expression" should be added to "primary" in A.8.4, not
"expression" in A.8.3. 

	 

	[SB] I question that. Let expands to a macro-like substitution
and with parentheses. And that substitution semantics is an essential
part of let. As in the example in the Motivation introduction, let c = a
+ b, when c is instantiated, a and b are size-extended to the size of
the context. Conversely, if a or b is bigger than the size of the other
nets and variables in the context of the let instance, then those other
nets and variables are size-extended to the size of a or b, whichever is
bigger. That is not consistent with regarding a let_expression as a
primary.

	 

	Regards,

	Shalom

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