RE: [sv-champions] Mantis 1728 - let

From: Brad Pierce <Brad.Pierce_at_.....>
Date: Thu Jul 24 2008 - 04:21:19 PDT
--- 6 ---

There are two module declarations that begin

 

    module m(input bit clock);

 

But there are, unfortunately, still no 2-state wires in SystemVerilog,
so these should be

 

    module m(input var bit clock);

 

--- 7 ---

"let_expression" should be added to "primary" in A.8.4, not "expression"
in A.8.3. 

 

n  Brad

 

From: owner-sv-champions@eda.org [mailto:owner-sv-champions@eda.org] On
Behalf Of Bresticker, Shalom
Sent: Thursday, July 24, 2008 6:57 PM
To: sv-champions@eda.org
Cc: sv-sc@eda.org
Subject: [sv-champions] Mantis 1728 - let

 

Hi, 

I have a small number of minor editorial comments on Mantis 1728: 

1. On p. 3, in 11.12, "A let declaration may be instantiated in other
expressions." It's not really the declaration that is being
instantiated. We don't use that terminology elsewhere, either. Better
would be, "A let construct may be instantiated ...".

2. A few lines after that: "while the scope of compiler directives is
global." This is not quite precise. Better would be "global within the
compilation unit," as in 3.12(d).

3. On p. 5, "It shall be an error, if the clock is required, but cannot
be inferred ...". The first comma should be deleted.

4. On p. 7, in example (e), the property declaration header should end
with a semicolon, in two places. 

5. The let keyword should be added to Table 21-5 in 21.14.7 also. 

Thanks, 
Shalom 

Shalom Bresticker 
Intel Jerusalem LAD DA 
+972 2 589-6582 
+972 54 721-1033 

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Received on Thu Jul 24 04:22:50 2008

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