Re: FW: Binding releated questionaires: Instantiation of VHDL-AMS design unit in SV (System Verilog)

In the Existing AMS user base, this has been the common understanding, so I'm not surprised at it..
and most simulator implementations only allow discrete (logic) value natures in the discrete time disciplines, and continuous value natures in the  continuous (time) domain disciplines.. except wreal   -- perpetuated by the current requirement to declare the domain with the discipline..

I think Kevin's description is probably more what it should be.. and some tool developers seem to indicate that this can be true..
a branch relationship V(a,b) <+ Rbranch*I(a,b); is uses a continuously valued discipline, in continuous time. 
but I really don't see a reason not to allow use off continuous value disciplines in discrete time..  but certain things would have to be specificed:
-- in VerilogAMS if two statements both contribute to a the voltage of a node, the actual voltage is the sum..
so if both an event driven (ie discrete time driver of the voltage of a net) and continuous(analog) block contribute to the voltage of the same net, the voltage a reciever sees should again be the sum..

I'll give two examples that should both work - borrowed from  VerilogAMS because, while I think VHDL & VHDL ams should be able to work inside SystemVerilog, I understand the Verilog side better.. and we can't really decide how to connect the VHDL ams ports until we have the Mixed signal side of SystemVerilog  worked out..

My example is a  D2A with a  common mode  FB circuit on the output stage..
// cmos_logic is a discrete discipline..
module dac_example (
  input  cmos_logic [7:0] code_in, // twos complement input
  input electrical  ibias,
  inout electrical vdd, gnd, 
 output electrical out_p, out_n
  parameter real Vlsb = 4m;
  parameter real vdssat = 0.5; //Thev. equiv model of Ibias diode connected mos
  parameter real rdssat = 200; // thev evquivalent model of ibias diode connected mos
  parameter real rload = 1K;
  real vcm; // value of an internal node
 always @(code) begin
    V(out_p,gnd) <+ 0.5*code*Vlsb;
   V(out_n,gnd) <+ -0.5*code*Vlsb;  // do we need a connect_module to control the edge rates as seen in the continuous domain?
end
analog begin
   V(ibias,gnd) <+ vdssat + rdssat*I(ibias,gnd);
   vcm = V(vdd,gnd) - 5*I(ibias,gnd)*rload  ; // ibias = 100u -> 0.5mA -> 0.5v below vdd
   V(out_p,gnd) <+ vcm;
   V(out_n,gnd) <+ vcm;
end

the way I would write this today under the delusions that electrical must be continous domain

module dac_example2 (
  input  cmos_logic [7:0] code_in, // twos complement input
  input electrical  ibias,
  inout electrical vdd, gnd, 
 output electrical out_p, out_n
  parameter real Vlsb = 4m;
  parameter real vdssat = 0.5; //Thev. equiv model of Ibias diode connected mos
  parameter real rdssat = 200; // thev evquivalent model of ibias diode connected mos
  parameter real rload = 1K;
 parameter real trf = 20p; // risefall time for a change in value
  real vcm; // value of an internal node
  real vcode = 0 ; // the differential value out of the DAC

always @(code) begin
   // maybe we add code to ensure we don't evaluate if there is an  X or Z input bit!
    vcode =  code*Vlsb; //again code is two's complement allowing negative result...
end
analog begin
    V(out_p,gnd) <+ 0.5*vcode;
   V(out_n,gnd) <+ -0.5*vcode;
    V(ibias,gnd) <+ vdssat + rdssat*I(ibias,gnd);
   vcm = V(vdd,gnd) - 5*I(ibias,gnd)*rload  ; // ibias = 100u -> 0.5mA -> 0.5v below vdd
   V(out_p,gnd) <+ vcm;// could do this all in one statement, but then its not quite as obvious that these are equivalent
   V(out_n,gnd) <+ vcm;
end

Kevin, does this agree with your concept of event domain continuous discipline drivers?

--

Since a "transition" function would be nicer to the analog solver than the sharp edges we might consider connect modules between the discrete (event) domain and the continuous time domain of the signal.. -- and since transition rates might vary with the port of the device (ie from a gate characterization) there should exist a way to look that up from the library characterization data (ie the .lib/.tlf  (timing) file) an event domain receiver wouldn't care, but a continuous domain receiver would need to be able to get the edge rates from the driver..

can we really segregate the analog(continuous value)  functions into drivers and receivers?

this is more useful where we want to insert "physical reality" into the net that connects them.. in a discrete (value and time) domain, this becomes simple "delay" - but this model of the real world is not really accurate in the nanoscale regime anyway..

To find the value for any given net you must convert all the drivers of the net to the same domain (preferably the most accurate - analog for a "mixed signal") resolve those driver values to get the net value, and then you can convert that value back into whatever the receivers require.

Hopefully these examples can extend our understanding of how to move forward here..

I've spent enough time on this for today!

 

Jonathan David
j.david@ieee.org
jb_david@yahoo.com
http://ieee-jbdavid.blogspot.com
Mobile 408 390 2425
Work:
jbdavid@scintera.com
http://www.scintera.com
408 636-2618

----- Original Message ----
From: K. Cameron [SV] <sv-xx@grfx.com>
To: sv-xc@eda.org
Cc: thalder@synopsys.com
Sent: Thursday, April 12, 2007 12:51:11 AM
Subject: Re: FW: Binding releated questionaires: Instantiation of VHDL-AMS design unit in SV (System Verilog)

Submission from Tapan Halder

....

 

Hi,

   In the original survey document for SV-AMS interoperability, we have not added any questions on SV/VHDL-AMS interaction. I would like to add few questions in the survey and also discuss VHDL-AMS related issue in our binding related discussion:

 

 

Here are some clarifications on terminologies used in AMS world :

I'd like to contest your definition of "discipline": It doesn't really indicate which domain a net belongs too, just which physical quantities it carries. I.e. if the discipline is electrical it will be voltage/current, but you can assign those values discretely from a digital domain or continuously from an analog domain. Or to put it differently: drivers and receivers belong to a domain (continuous or discrete), and nets have a discipline.

Similarly a "mixed signal" net is one with both continuous and discrete drivers and/or receivers.

A "receiver" is the interface by which values are passed from a net to a process, as a "driver" is the interface by which values are passed to a net from a process. Receivers are significant in AMS because that's where value conversion (usually a2d) takes place.

A "driver" in a continuous process is also known as a "contribution".

Kev.
 

Terminology

Connect module	A special module that converts signal values from discrete (digital) domain to continuous (analog) domain and vice versa. Instances of connect modules are auto-inserted by the simulator across analog-digital boundaries.
Continuous domain	The continuous domain represents the analog simulation space in which signal values vary continuously.
Discipline	The property of a net that dictates the domain (discrete or continuous) in which that particular net will be simulated. Each discipline can bind a nature to its potential and flow.
Discrete domain	The discrete domain represents the digital simulation space in which signal values change instantaneously, but only at integer multiples of a minimum resolvable time.
Terminal	A combination of two quantities, the reference and contribution quantities, that is used to model a node in a given electrical circuit or any energy domain such as electrical, magnetic, thermal, rotational etc.. This is a VHDL-AMS terminology related to analog node.
Quantity	VHDL-AMS quantity represents analog values.
Nature	A VHDL-AMS terminal is of a specified nature, which defines the continuous values associated with a terminal. The nature represents the energy domain (such as electrical, magnetic etc.) for the terminal.
Mixed-signal net	A net that contains at least one digital and one analog net segment.

 

Survey Questionaire :

 

================================================================

Section 4: AMS

================================================================

 

 4.1    What kind of Analog design unit would you like to instantiate

        in SystemVerilog

[1] 4.1.1  SPICE

[1] 4.1.2  VERILOG-AMS

[] 4.1.3  Others. please specify

 

 Add :

 

  [] 4.1.3  VHDL-AMS

  

  [] 4.1.4 Others. Please specify

 

 

[] 4.22 How important it is to formalize the rule to connect a VHDL-AMS

        “terminal” port to a VERILOG-AMS analog node (node having continuous

         discipline)

 

[] 4.23 How important it is to formalize the rule to connect a VHDL-AMS “terminal”

        port to a System Verilog digital net.

 

 

 

 

 

 

Binding ( or rather type) related questions to be discussed:

 

 

1.    Come up with the compatibility rules for VHDL-AMS nature and the corresponding Verilog-AMS discipline for the natures declared in the IEEE.electrical_systems package

 

2.    Is it OK to connect a VHDL-AMS terminal to a SV digital net? Inside VHDL-AMS, a terminal can be connected only to a terminal. However, in VERILOG-AMS, language does allow an analog node to be connected to a digital net and the language provides a mechanism to automatically insert a connect module (D2A or A2D converter) at Analog/Digital boundary. Which rule to follow : VERILOG-AMS or VHDL-AMS?

 

 

Thanks

 

 

= Tapan =

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