Re: FW: Binding releated questionaires: Instantiation of VHDL-AMS design unit in SV (System Verilog)

>
> Submission from Tapan Halder
> ....
>
>  
>
> Hi,
>
>    In the original survey document for SV-AMS interoperability, we 
> have not added any questions on SV/VHDL-AMS interaction. I would like 
> to add few questions in the survey and also discuss VHDL-AMS related 
> issue in our binding related discussion:
>
>  
>
>  
>
> Here are some clarifications on terminologies used in AMS world :
>
I'd like to contest your definition of "discipline": It doesn't really 
indicate which domain a net belongs too, just which physical quantities 
it carries. I.e. if the discipline is electrical it will be 
voltage/current, but you can assign those values discretely from a 
digital domain or continuously from an analog domain. Or to put it 
differently: drivers and receivers belong to a domain (continuous or 
discrete), and nets have a discipline.

Similarly a "mixed signal" net is one with both continuous and discrete 
drivers and/or receivers.

A "receiver" is the interface by which values are passed from a net to a 
process, as a "driver" is the interface by which values are passed to a 
net from a process. Receivers are significant in AMS because that's 
where value conversion (usually a2d) takes place.

A "driver" in a continuous process is also known as a "contribution".

Kev.
 
>
>
>     *Terminology*
>
> *Connect module*
>
> 	
>
> A special module that converts signal values from discrete (digital) 
> domain to continuous (analog) domain and vice versa. Instances of 
> connect modules are auto-inserted by the simulator across 
> analog-digital boundaries.
>
> *Continuous domain*
>
> 	
>
> The continuous domain represents the analog simulation space in which 
> signal values vary continuously.
>
> *Discipline*
>
> 	
>
> The property of a net that dictates the domain (discrete or 
> continuous) in which that particular net will be simulated. Each 
> discipline can bind a nature to its potential and flow.
>
> *Discrete domain*
>
> 	
>
> The discrete domain represents the digital simulation space in which 
> signal values change instantaneously, but only at integer multiples of 
> a minimum resolvable time.
>
>  
>
> *Terminal*
>
> 	
>
> A combination of two quantities, the reference and contribution 
> quantities, that is used to model a node in a given electrical circuit 
> or any energy domain such as electrical, magnetic, thermal, rotational 
> etc.. This is a VHDL-AMS terminology related to analog node.
>
>  
>
> *Quantity*
>
> 	
>
> VHDL-AMS quantity represents analog values.
>
> *Nature*
>
> 	
>
> A VHDL-AMS terminal is of a specified nature, which defines the 
> continuous values associated with a terminal. The nature represents 
> the energy domain (such as electrical, magnetic etc.) for the terminal.
>
> *Mixed-signal net*
>
> 	
>
> A net that contains at least one digital and one analog net segment.
>
>  
>
> Survey Questionaire :
>
>  
>
> ================================================================
>
> Section 4: AMS
>
> ================================================================
>
>  
>
>  4.1    What kind of Analog design unit would you like to instantiate
>
>         in SystemVerilog
>
> [1] 4.1.1  SPICE
>
> [1] 4.1.2  VERILOG-AMS
>
> [] 4.1.3  Others. please specify
>
>  
>
>  Add :
>
>  
>
>   [] 4.1.3  VHDL-AMS
>
>   
>
>   [] 4.1.4 Others. Please specify
>
>  
>
>  
>
> [] 4.22 How important it is to formalize the rule to connect a VHDL-AMS
>
>         "terminal" port to a VERILOG-AMS analog node (node having 
> continuous
>
>          discipline)
>
>  
>
> [] 4.23 How important it is to formalize the rule to connect a 
> VHDL-AMS "terminal"
>
>         port to a System Verilog digital net.
>
>  
>
>  
>
>  
>
>  
>
>  
>
>  
>
> Binding ( or rather type) related questions to be discussed:
>
>  
>
>  
>
> 1.    Come up with the compatibility rules for VHDL-AMS nature and the 
> corresponding Verilog-AMS discipline for the natures declared in the 
> IEEE.electrical_systems package
>
>  
>
> 2.    Is it OK to connect a VHDL-AMS terminal to a SV digital net? 
> Inside VHDL-AMS, a terminal can be connected only to a terminal. 
> However, in VERILOG-AMS, language does allow an analog node to be 
> connected to a digital net and the language provides a mechanism to 
> automatically insert a connect module (D2A or A2D converter) at 
> Analog/Digital boundary. Which rule to follow : VERILOG-AMS or VHDL-AMS?
>
>  
>
>  
>
> Thanks
>
>  
>
>  
>
> = Tapan =
>
>
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