Re: Instantiating VHDL components in SystemVerilog.

Hi Logie,

I appreciate you taking the first steps.  This is actually not quite 
what we agreed to do.  I had proposed starting specifically with 
SV-VHDL, but the consensus was to begin with developing a framework for 
all languages along the lines of earlier discussions.  We did what 
aspect to start with, e.g., simulation cycle semantics, binding, PLI, 
etc.  Binding indeed is the place we agreed to start.  We discussed 
whether data types were a part of that discussion and agreed that, while 
related, it is a separable aspect of the framework.  With respect to 
binding, we agreed that VAMS brings no special issues and that 
restricting the problem to SV-VHDL-SC is sufficient. If  this does not 
sound correct, we can confirm when we accept the minutes.  It would 
certainly be useful to produce those minutes closer to when we have the 
meeting than just before the next one, at least for the sake of my 
memory. ;)

With respect to the questions, you propose here.  I think 3.1 is 
appropriate as are the additional ones you've added.  I will send along 
some questions in a separate email.

Regards,
John




Logie Ramachandran wrote:
> Hi Team,
>
> We decided to address SV->VHDL instantiation as our first
> topic. We also decided to have a set of questions that
> we would like answered as part of this topic. 
>
> I have pulled out some of the questions from 
> the survey that pertains to this topic. 
>
>     3.1    What kinds of items would you like to be able to 
>            instantiate across VHDL, SystemVerilog boundary
>     3.3    What kinds of objects would you like to connect in an
>            instantiation that crosses SystemVerilog-VHDL boundary
>     3.4    What kinds of data types would you like to see supported
>            on "parameters/generics" at the SystemVerilog-VHDL
>            boundary
>     3.4b   Please list any data type mappings (e.g. VHDL std_ulogic
>            to Verilog logic) that are particularly important
>     3.5    What kinds of data types would you like to see supported
>            on "nets/signals" at a language boundary?
>     3.5b   Please list any data type mappings (e.g. VHDL std_ulogic
>            to Verilog logic) that are particularly important
>     3.6    What kinds of data types would you like to see supported
>            on "variables" at the SystemVerilog/VHDL language boundary?
>     3.6b    Please list any data type mappings (e.g. VHDL std_ulogic
>            to Verilog logic) that are particularly important
>
> Additional questions that are focused on SystemVerilog syntax.
>    
> Q1. What is the syntax for instantiating a VHDL module/entity inside
>     SystemVerilog? 
>
> Q2  Should type parameters be disallowed for VHDL instantiations?
>     
> Q3. What are the different types of parameters that will be allowed on
> the
>     instantiation statement.  
>
> Q4. In a multilanguage environment do we need to define
>     special attributes in the instantiation  that
>     indicates if a module is coming from (a) different language, 
>     (b) which one? 
>
> Q5.  Will extern module declarations be extended for VHDL modules?
>
> Q6.  SystemVerilog allows instantiation using 
>      i. positional port connections
>     ii. named port connections
>    iii. implicit .name port connections
>     iv. implicit *.port connections
>
> Q7. How will the SV port connection rules be modified for instantiating
>     a VHDL component. 
>   
> Q8. What kind of expressions will be allowed (if any) on the port 
>     connections. (eg. partselects, concats). 
>
> Please add other questions that pertain
> to instantiating VHDL in SystemVerilog 
>
> Thanks
>
> Logie. 
>
>   

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