Survey Feedback from Top Lertpanyavit

 

-----Original Message-----
From: Lertpanyavit, Thanapoom [mailto:thanapoom.lertpanyavit@intel.com] 
Sent: Thursday, March 01, 2007 1:58 PM
To: Logie Ramachandran
Subject: RE: SystemVerilog Interoperability survey

Hi Logie,

Here is my input. I'm primarily concerned about the
SystemVerilog/Verilog-AMS side of interoperability, so did not answer
the other portions concerning VHDL or SystemC.


Thanks,
Top Lertpanyavit


-----Original Message-----
From: owner-sv-xc@server.eda.org [mailto:owner-sv-xc@server.eda.org] On
Behalf Of Logie Ramachandran
Sent: Wednesday, February 28, 2007 11:22 AM
To: sv-xc@server.eda.org; sv-bc@server.eda.org; sv-ac@server.eda.org;
sv-ec@server.eda.org; sv-cc@server.eda.org; ieee1800@server.eda.org
Subject: SystemVerilog Interoperability survey


The SV-XC committee is soliciting your inputs on SystemVerilog
Interoperability with VHDL, AMS and SystemC. The committee has
prepared a survey in order to gather user requirements and help
focus the standardization activities based on your requirements. 

The survey is available at
http://www.eda-stds.org/sv-xc/otherdocs/survey1.0.txt

This is a simple text file. You can save it on your desktop
and fill it out with your normal editor. 

The instructions are provided in the survey. Please send your
feedback to the committee by emailing to sv-xc@eda.org. If you
like you can also send your completed survey to logie@synopsys.com
or somdipta@ti.com

We would appreciate your response by 3/15/2007. 


Somdipta Roy (TI)
Logie Ramachandran (Synopsys) 

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