[P1800] Re: IEEE 1800-2007

Hi Lisa,

The IEEE used to have what is known as "1800-2008 draft 3a" for sale. I just
spent some time trying to find it in the IEEE web pages.

Back in October, Dave Rich pointed to the following information for it. I was
not able to find this document on the IEEE web site.

    ISBN (13 DIGIT): 978-0-7381-5616-3  <--- Dave pointed to this one

I was able to find the following. The publication date is showing up
as 1/1/2007. Draft 3a came out on May 31, 2007. The page count is shown as
being 652. My copy of 1800-2005 has 648 pages. 1800-2008 draft 3a is over
1000 pages (it is a merge of 1364 and 1800).

    ISBN (13 DIGIT): 978-0-7381-5726-9  <--- I found this one

The document I found is also referred to as

    "62530: 2007 (E) Standard for SystemVerilog-Unified Hardware Design,
     Specification, and Verification Language"

     Product Number: STDPD95745

Based on what I am seeing, this doesn't look like 1800-2008 draft 3a.
I'm not sure what happened to the document that Dave Rich had previously
found on the IEEE web page, but it now looks like it is gone and we now have
this copy of 1800-2005 in its place.

There is a copy of 1800-2005 on the IEEE web site. It shows a publication
date of 1/1/2005. That is not when the document came out. It was more like
November 2005. So it looks like the dates aren't quite right on the IEEE
web pages.

    ISBN (13 DIGIT): 978-0-7381-4811-3
    Product Number:  STDRE95376
    Non-Member Price: $55.00           Note that the 2007 version is much more.

    The description mentions: "Replaced by 62530(E):2007."

If you plan to do any searches within these web pages for these documents,
I suggest that you use verilog as a keyword. It appears that in some
places SystemVerilog is one word and in other places it is two words.

Neil





Lisa Piper wrote:
> Hi Neil,
> 
> It was pointed out to me that there exists an IEEE Std 1800-2007 on the 
> IEEE web site.   Do you know how this is this different from the IEEE 
> 1800-2005?   Is it just editorials or is it the combined Verilog + 
> SystemVerilog?
> 
> Lisa
> 

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