RE: [P1800] P1800 SystemVerilog Ballot Draft (4.0) is ready

From: Francoise Martinolle <fm_ f rom>
Date: Wed Feb 16 2005 - 08:44:21 PST
 
I also noticed that the bookmarks are not provided for the
chapters. I only have bookmarks for the sub-sections...

Francoise
    '
-----Original Message-----
From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On Behalf Of
Shalom Bresticker
Sent: Wednesday, February 16, 2005 11:06 AM
To: Johny Srouji
Cc: Rich, Dave; ieee1800@eda.org; stuart@sutherland-hdl.com
Subject: Re: [P1800] P1800 SystemVerilog Ballot Draft (4.0) is ready

I don't see the problem.

Clause 2 is Normative References (IEEE rules).

The other clauses were bumped by 1.

Shalom


Johny Srouji wrote:

>
> Dave, you're right.
> Section 2 is supposed to be literals (which is marked as section 3).
>
> Stu, can you please look into this ASAP? We may need to fix the ballot 
> draft for this.
>
> thanks,
>
> --- Johny.
>
>
>
>
> "Rich, Dave"
                                           Johny Srouji/Austin/IBM@IBMUS,
  <Dave_Rich@mentorg.com>               To <ieee1800@eda.org>

  02/16/2005 09:22 AM                   cc <stuart@sutherland-hdl.com>

                                   Subject RE: [P1800] P1800 SystemVerilog
                                           Ballot Draft (4.0) is ready

>
>
>
> BTW, are my eyes failing me, or is this draft missing section 2? (or 
> maybe both).
>
> I think section 3 was supposed to be section 2.
>
> Dave
>
>
>
>
> ----------------------------------------------------------------------
> ---------
>
>
> From: owner-ieee1800@eda.org [mailto:owner-ieee1800@eda.org] On Behalf 
> Of Johny Srouji
> Sent: Monday, February 14, 2005 8:48 AM
> To: ieee1800@eda.org
> Subject: [P1800] P1800 SystemVerilog Ballot Draft (4.0) is ready
>
>
> Hi All,
>
> Please note that P1800 SystemVerilog Ballot draft is ready and was 
> uploaded (thanks to Dennis) to our web site under:
> http://grouper.ieee.org/groups/1800/private/P1800-draft4_SystemVerilog
> _LRM.pdf
>
> This version is a clean draft (no colored text, change bars, etc) and 
> it will be our draft for Ballot.
>
> I would like to use this opportunity to thank you all for the hard 
> work in enabling this, and to our technical editor, Stu Sutherland, 
> who has been making excellent progress and follow-up on all of our drafts.
>
> Enjoy,
>
> --- Johny.

--
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Verification Methodology                    Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                 Fax: +972 9  9522890
POB 2208, Herzlia 46120, ISRAEL                     Cell: +972 50 5441478

[ ]Freescale Internal Use Only      [ ]Freescale Confidential Proprietary
Received on Wed Feb 16 08:44:31 2005

This archive was generated by hypermail 2.1.8 : Wed Feb 16 2005 - 08:44:33 PST