SystemVerilog Errata ratification vote

Hi All,

Although it was decided in the WG meeting to close voting on the Errata
list ratification by Oct'18, I decided to extend the voting period by
one week (which would then become 14 days). This is mainly because I
still don't have 50% return and to follow the 14 days rule in our P&P.

Attached is an HTML file indicating votes I received so far. All those
who did not cast their vote yes, I URGE you to do so ASAP. We are all
aware of the aggressive schedule we would like to meet (this would serve
both EDA and users) and it is critical to finalize a closure on this
bulk of issues so that Karen can proceed or determine further action
items.

Voting will close next Monday, October 25.

p.s. I captured Intel vote as "Yes" but I will not count it for the 50%
votes (the chair only votes to break a tie)

Regards,

--- Johny.