RE: [sv-dc] Re: Clarification for mantis 3724

Hi all:

Gord, thanks for the feedback. I have made changes that I believe are in line with your comments. I have uploaded a new version (_ver5) on mantis ( http://www.eda-twiki.org/svdb/view.php?id=3724 ). If everyone could give this latest version a quick look and provide feedback then I will call for an e-mail vote tomorrow.

Thanks,
Scott

From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of Gordon Vreugdenhil
Sent: Wednesday, September 21, 2011 8:40 PM
To: Little Scott-B11206
Cc: Vreugdenhil, Gordon; sv-dc@eda.org
Subject: [sv-dc] Re: Clarification for mantis 3724

I'm fine with either sentence; the second is a bit more general so I'd probably go with that. I'm not sure that the "data types" part of the sentence is needed; I think that is redundant with net types since the only way the "data type" could be different is if a different nettype was in play. I don't think the redundancy is wrong per se but it might make a reader wonder if there is some way to get a data type difference without a net type difference (which there isn't).

The example is fine except for one detail; the line:
    module rlMod(input interconnect iBus,...);
needs to be:
    module rlMod(input interconnect [0:1] iBus,...);
                                                               ^^^^^

Gord.

On 9/21/2011 10:12 AM, Little Scott-B11206 wrote:
Hi Gord:

In the meeting today there was a desire to have some additional clarification of non-homogenous interconnect arrays. Steven suggested adding a sentence along the line of the one in green below.

<from second paragraph in 6.6.8>
An interconnect net or port shall not be used in any expression other than a net_lvalue expression in which all nets or ports in the expression are also interconnect nets. A concatenation of interconnects shall be considered a valid port expression even if different operands in the concatenation are resolved to different net types or data types.

In addition to this we thought it would add clarity to show a non-homogenous interconnect array in an example. An example of this type is shown below.

Steven also conjectured that we could change the additional statement above and possibly clarify both points without adding an additional example. A statement that might be adequate would be something like: An interconnect array shall be considered valid even if different bits in the array are resolved to different net types or data types.

Your thoughts?

This seems to be the last sticking point. The hope is to get this item resolved soon and then call for an e-mail vote on 3724.

Thanks,
Scott

Example illustrating non-homogenous interconnect arrays

import NetsPkg::*;
module top();
  interconnect [0:1] iBus;
  lDriver l1(iBus[0]);
  rDriver r1(iBus[1]);
  rlMod m1(iBus,...);
endmodule : top

module lDriver(output logic out);
  ...
endmodule

module rDriver(output realNet out);
  ...
endmodule

module rlMod(input interconnect iBus,...);
  lMod l1(iBus[0],...);
  rMod r1(iBus[1],...);
endmodule

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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com<mailto:gordonv@model.com>
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