[sv-dc] RE: Poll for follow-on work

Hi Jim:

Yes, tran-type gates can be implemented in the user space. Tran gates are already present in SV, and I think it would be nice to extend them to user defined nettypes. In the simple case where a user wants a mechanism to "turn off" a driver with a switch, then tran gates are available. They won't meet all "switch" needs, but I think they will be a useful addition.

Thanks,
Scott

> -----Original Message-----
> From: Lear, Jim [mailto:Jim.Lear@cirrus.com]
> Sent: Monday, May 09, 2011 10:52 AM
> To: Little Scott-B11206; 'sv-dc@eda.org'
> Subject: RE: Poll for follow-on work
>
> Hi Scott,
>
> Perhaps I'm misunderstanding why we need item 3, at least initially.
> With resolved signals, tran gates can now be implemented in the user
> space. For example, the Thevenin resistor model (see the VHDL model I
> provided) can be changed so resistance switches between 0 and infinity
> controlled by a third "gate" input.
>
> Kindest Regards,
> Jim Lear
> Cirrus Logic
> (512) 851-4612
> (512) 293-7248 (mobile)
>
>
> -----Original Message-----
> From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of
> Little Scott-B11206
> Sent: Monday, May 09, 2011 9:44 AM
> To: sv-dc@eda.org
> Subject: [sv-dc] Poll for follow-on work
>
> Hi all:
>
> Below are the list of items I have collated as possible next step work
> items. Please respond with your top 2 items. Also, please specify if
> you are willing to participate in proposal writing for a specific item.
> Write-in options are welcome. Please respond by Monday, May 16.
>
> 1. Generic interconnect
> 2. Built-in/standard nettypes
> 3. Nettype compatible tran gates
> 4. Late binding/nettype override
> 5. VPI model for nettypes
>
> Thanks,
> Scott
>
>
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