[sv-dc] Discipline Access Functions

Just a note:

If disciplines are adopted, then you can use the access functions (V,I etc) to get the wreal behavior. E.g. rather than declare a wreal you just declare a wire/reg and use an access function to assign to it, or read from it:

  wreal wr;
  always @(clk) wr = 0.0;

becomes

  wire w; // assume default discipline is Electrical
  always @(clk) V(w) = 0.0;

which you could mix with other assignments like -

  w= 1'bz;

V(w) in an expression rather than the LHS of an assignment gives you the wire voltage as a real.

The purpose is somewhat clearer with the access functions than without. You could use "I(w)" for currents - which would be understood to be additive.

If you have an operator (say ->) to access the discipline attributes of the wire, and those include nominal power supplies, then you could write code like:

 wire q;
 always @(clk)
    V(q) = d
            ? q->vdd
            : q->vss;

Kev.

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