[sv-dc] resolution schemes

Just a further remark on resolution:

i.m.o one can distinguish at least two kinds of real-value resolution:

1) signalflow application: that is kind of the traditional application,
   that was up to now addressed by (primitive built-in or VHDL)
resolution functions.
   If we add a state/timing to this kind of resolution, it can cover
many important scenarios in practice,
   e.g. this enables the description and verification of
inertial/delayed connections and high impedance nodes.

2) pseudo-analog (conservative, lumped) application:
   indispensable for resolution of backannotated networks and for
real-value multi-driver scenarios,
   that have to be treated in an "analog way". This application e.g.
might use Thevenin/Norton description.
   Requires a considerable amount of additional computation efforts.
   If we add a state/timing to this kind of resolution, we can vastly
speed-up this procedure
   and/or enhance accuracy. Otherwise a fastSpice/AMSflow might be
faster (but more expensive).

Thanks,
       Achim

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