[sv-dc] RE: Questions for the SV-DC meeting on 2010-10-20

Here are some answers:

> 1. I understand that SystemVerilog supports real variables attached to
> ports. 1.1 In this case, how is resolution done?

[SB] SV allows only one driver on real ports, so no resolution is needed.

> 1.2 Also is directionality supported on such ports? And if so what are
> the semantics for input, inout, output?

[SB] input and output are allowed for reals, but not inout. ref is also allowed.
 
 
> 2. I understand that SystemVerilog supports structs. Can there be real
> fields in these structs?

[SB] Yes.
 
 
> 3. Using struct mechanism, what does SystemVerilog support in terms of
> "Aggregate nets with real valued components including constructs such
> as vectors, static arrays, structs, unions" - [Ref R05]

[SB] What is the question?

 
> 4. I understand that SystemVerilog supports struct variables attached
> to ports. In this case, how is resolution done?

[SB] A struct can be a net or a variable. It can be a net if all the members of the struct are 4-state integral types. If it is a variable, only one driver is allowed. If it is a net, it is treated like a regular net.
 
 
> 5. Does SystemVerilog support any form of "type conversion mechanisms
> to enable connection of nets of different, yet compatible, types and
> structures, including connection of aggregate nets" - [Ref R11]

[SB] Not sure of the question.

Regards,
Shalom

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