[sv-dc] RE: Questions for the SV-DC meeting on 2010-10-20

Scott
Here are my questions on the SystemVerilog reals and UDTs - I am hoping that the answers to these will be helpful for the committee have a common
background of relevant SystemVerilog knowledge.

I was unable to send out these questions yesterday so I don't expect them to be answered before or during tomorrow's SV-DC meeting - however great if they can be. If not, hope that they can be answered on the reflector after the tomorrow's meeting.

Thanks,
--Martin

1. I understand that SystemVerilog supports real variables attached to ports. 1.1 In this case, how is resolution done?
1.2 Also is directionality supported on such ports? And if so what are the semantics for input, inout, output?
 

2. I understand that SystemVerilog supports structs. Can there be real fields in these structs?
 

3. Using struct mechanism, what does SystemVerilog support in terms of "Aggregate nets with real valued components including constructs such as vectors, static arrays, structs, unions" - [Ref R05]

4. I understand that SystemVerilog supports struct variables attached to ports. In this case, how is resolution done?
 

5. Does SystemVerilog support any form of "type conversion mechanisms to enable connection of nets of different, yet compatible, types and structures, including connection of aggregate nets" - [Ref R11]

-----Original Message-----
From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of Little Scott-B11206
Sent: Wednesday, October 13, 2010 9:07 AM
To: sv-dc@eda.org
Subject: [sv-dc] Questions for the SV-DC meeting on 2010-10-20

Hi all:

In the last meeting it was decided that in our upcoming meeting on 2010-10-20 we would have a presentation regarding wreal from Cadence.
If there are questions regarding the current capabilities of reals and/or aggregates within SystemVerilog we would do our best to discuss those questions.

If you have items you would like to see Cadence cover regarding wreal or questions regarding the current capabilities or reals and/or aggregates within SystemVerilog please send them to the list by Monday evening.

Thanks,
Scott

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