Re: [sv-dc] Draft of SV-DC roadmap

From: Gordon Vreugdenhil <gordonv@model.com>
Date: Tue Sep 07 2010 - 07:20:09 PDT

R05-R09 covers aggregate (user defined) types and resolutions.

It is actually still to be determined if a 4-state real
value type and related net type need to be directly part
of the work. It is listed to ensure that any *mechanism*
would be able to describe that simpler model and as a
separate question whether it is still desirable to have
the simple case directly described versus through a more
general mechanism.

Once we have the general mechanism defined, we can discuss
whether the special case 4-state real should be added as well.

Gord.

On 9/6/2010 8:46 PM, Kevin Cameron wrote:
>
> I would prefer to see something like "user defined type" used instead of
> "real valued". The aim (I think) is to support low level hardware
> modeling in ways that are not currently supported, which would include
> RF modeling with types other than simple real values. SV has a whole
> class type scheme already, seems limiting ourselves to "real valued"
> probably won't simplify much.
>
> Is the "X" and "Z" stuff really a "must"?
>
> Might want to add a "could" or "should" for power supply connectivity,
> and for back-annotation.
>
> Kev.
>
>
> On 09/06/2010 08:01 PM, Little Scott-B11206 wrote:
>> Hi all:
>>
>> I have attached a draft of the SV-DC roadmap. We will discuss this in
>> the SV-DC meeting on Wednesday. If you believe that the roadmap needs
>> to be changed and would like to discuss it on the list prior to the
>> meeting please send specific suggestions.
>>
>> Thanks,
>> Scott
>>
>>
>
>

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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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Received on Tue Sep 7 07:20:31 2010

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