Re: [sv-dc] Power related proposals UPF/CPF

Simulating power is an analog/mixed-signal problem but power-management
is mostly being done for digital designs, so it spans SV and AMS. Since
AMS missed the window for incorporation into Verilog before it moved to
the IEEE, that means this issue now spans a bunch of committees and is
pretty difficult to fix on the HDL side - hence folks use UPF/CPF in
conjunction with Verilog through the digital flow. This falls into the
pattern of "new problem -> new committee -> new language", which usually
ends up with "lets donate this to the *Verilog* effort", which is why it
always takes longer than it should and SV is a mess.

I think the post-synthesis part of flow is seriously broken, all the
information in UPF/CPF should be converted into proper HDL constructs by
synthesis tools so that it can be verified thoroughly without having to
resort to Spice-level simulation.

Kev.

On 08/12/2010 05:41 AM, Little Scott-B11206 wrote:
> Hi Kevin:
>
> For digital circuits many folks are adopting a methodology that includes
> the use of UPF/CPF. It seems to me that if one portion of the design
> (maybe the largest portion) is checking power domain concerns with
> UPF/CPF then it makes sense to try and extend UPF/CPF to handle the
> analog portion as well. What is your take here?
>
> Thanks,
> Scott
>
>
.....

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