RE: [sv-dc] Power related proposals

Hi Kevin:

For digital circuits many folks are adopting a methodology that includes
the use of UPF/CPF. It seems to me that if one portion of the design
(maybe the largest portion) is checking power domain concerns with
UPF/CPF then it makes sense to try and extend UPF/CPF to handle the
analog portion as well. What is your take here?

Thanks,
Scott

> -----Original Message-----
> From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of
> Kevin Cameron
> Sent: Wednesday, August 11, 2010 6:40 PM
> To: sv-dc@eda.org
> Subject: Re: [sv-dc] Power related proposals
>
>
> Just a note:
>
> In AMS there are a few places you can hang information about nominal
> supply voltages -
>
> In the wire disciplines
> Explicitly in modules
> Explicitly in connect modules
> Explicitly in connect module parameters (through connection rules)
> Global variables
>
> If you are interested in applying rules about voltage domains and
> domain
> crossing - e.g. spotting accidental connection of 1V to 2V logic
> without
> a level shifter - then you probably want to put the information in the
> disciplines, however I don't think there is any official syntax for
> getting at it at the moment.
>
> I like to view disciplines as a "technology type", where you can hang
> attributes about usage for different tools. Drivers and receivers on a
> net must have a common base discipline (e.g. Electrical), but can have
> different individual attributes, e.g. the base discipline might define
> Vdd as 1V, derived disciplines used for different receivers might
> indicate different threshold voltages for logic levels - where the
> threshold voltage is an attribute of the technology not the simulation
> method (i.e. doesn't matter if you are using logic, wreal or
> PWL/continuous).
>
> Things you might like to be able to do are:
>
> Use the discipline info in assertions
> - e.g. is the actual supply voltage within range
>
> Use threshold info in different models
> - e.g. in connect modules and resolution functions
>
>
> Discipline types are significant even if nothing is attached to a net
> in
> a particular module, i.e. you shouldn't try and connect (say)
something
> electrical to something mechanical.
>
> Kev.
>
> On 08/11/2010 09:53 AM, Kevin Cameron wrote:
> > http://www.verilog.org/mantis/view.php?id=1754 < specifying power
> > connections
> > http://www.verilog.org/mantis/view.php?id=2343 < AMS fix
> >
> > SDF is pretty useless in this area, so here's an alternative -
> >
> >
>
http://www.eda-twiki.org/cgi-bin/view.cgi/VerilogAMS/BackAnnotationProposal
> >
> > - works for ECOs too.
> >
> > Note: this stuff is mostly about elaboration/connectivity and not
> > run-time behavior.
> >
> > Kev.
> >
> >
> >
> >
>
>
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