AW: Strawman Ideas for SV-DC

Hi John,

> John: > Why not simply adopt (maybe by stages) the Accellera Verilog-A/MS
Std?
What aspects do you mean, are you thinking of the connect module insertion ?

> John: > You would not want a simulation kernel which included analog
scheduling.
Absolutely, no "analog" scheduling is required indeed, just event-based
steps.

> John: > anyway: It would be very bad for digital performance.

If a mixed-signal(real-value) verification needs custom resolution with
powerful datatypes
and the user is not supplied with these features, a fast, but evtl.
meaningless
simulation does not help very much.
The simulation must be skipped (which is even faster ;)
and certain aspects will stay unverified.

Regards,
        Achim

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