Re: Strawman Ideas for SV-DC

Hi.

Why not simply adopt (maybe by stages) the Accellera
Verilog-A/MS Std?

You would not want a simulation kernel which included
analog scheduling, anyway: It would be very bad for
digital performance.

Popular verilog simulators such as VCS already have cut
out correct switch-level and strength simulation because
of poor performance on large designs.

On 07/14/2010 08:43 AM, Arturo Salz wrote:
> Attached are some preliminary ideas on how to achieve the short term objectives of the SV-DC committee. We would like to share these with the SV-DC committee.
>
> Arturo
>
>

-- 
      John Michael Williams
      Senior Adjunct Faculty
Silicon Valley Technical Institute
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.