FW: [sv-bc] Proposed SV-DC scope

FYI, Brad Pierce made a succinct link to the Google doc of the scope.

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Friday, May 21, 2010 3:37 PM
To: sv-bc@eda.org
Subject: [sv-bc] Proposed SV-DC scope (Was: SV-DC meeting 2010-05-25)

http://bit.ly/cWIN31

For info about the first SV-DC meeting, see

   http://www.eda-twiki.org/sv-dc/hm/0001.html

-- Brad

-----Original Message-----
From: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] On Behalf Of
Havlicek John-R8AAAU
Sent: Friday, May 21, 2010 1:22 PM
To: sv-dc@eda.org
Subject: SV-DC meeting 2010-05-25

Hi Folks:

The next meeting of SV-DC will be for one hour on Tuesday, May 25 at
10:00 CDT (UTC-05:00) to finalize a scope description to be presented to
the P1800 Working Group on Thursday, May 27.

Below is a draft statement of scope in which we have tried to
incorporate inputs we have heard from individuals and in the discussion
in the initial meeting. This draft is also in a Google doc at the
following link

https://docs.google.com/document/edit?id=1NK-gDXzTgtZOxBicT-n0sSG7ZHfEsY
9nj5fk08Yw_7g&hl=en

so that we can edit it during the meeting. The Google doc should be set
up so that anyone can view it.

Please feel free to send feedback on the draft prior to the meeting.

Dialin information for the meeting is at the bottom.

Thanks,
John & Scott

Draft SV-DC Scope:

The SV-DC committee will investigate and recommend a roadmap for
discrete modeling features within SystemVerilog. Limiting the scope to
discrete modeling means there is not an intention to bring the analog
solver into SystemVerilog. The near term roadmap will likely include
nets and ports of generic data types, resolution functions, and type
conversion mechanisms. Longer term, the roadmap may include features
for piece-wise linear waveform definition and support for several
modeling styles (e.g., timed data driven, signal flow, modeling with
restricted conservative linear networks). It is expected that these
features can exist in SystemVerilog without a SystemVerilog/Verilog-AMS
merger.

The primary use case motivating this work is the need for high speed AMS
models. These models may be used in a plug and play environment where
Spice or Verilog-AMS models are replaced by faster discrete models based
on need.

The roadmap will focus on the items to be completed within the 2012 PAR,
but will also provide vision for future directions. It will identify
the new discrete modeling features and describe how they will interact
with current SystemVerilog features. It may also include
recommendations of how these features interact with VHDL and/or
Verilog-AMS. The initial roadmap will be completed prior to the P1800
WG meeting on August 12, 2010.

Dialin information:
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