Re: AW: AW: SV-DC meeting 2010-05-25

<grin>

We are definitely wording this for different audiences -- I am
wording this for the digital simulation reader who will (generally)
panic at any hint of analog; you are wording this for the analog/ams
reader who understands the implications of the terms you are using.
I suspect that the "digital centric" phrasing might be better since
the scope document is targeted at the digital (SV) community.

I'm not going to oppose your wording if that is the preference but
do want to make sure we understand each other's relative biasing.

Gord

Achim Bauer wrote:
> In fact this is what I wanted to indicate with the term "functional".
> In the analog world you are often using the terms "natural" or "lumped"
> for models with conservative behavior (low abstraction).
> Highly abstracted models for discrete/digital simulators are often called
> functional or algorithmic (or signalflow if they contain f(t) expressions).
>
> Achim
>
>
> -----Ursprüngliche Nachricht-----
> Von: Gordon Vreugdenhil [mailto:gordonv@model.com]
> Gesendet: Dienstag, 25. Mai 2010 16:27
> An: Achim Bauer
> Cc: 'Havlicek John-R8AAAU'; sv-dc@eda.org
> Betreff: Re: AW: SV-DC meeting 2010-05-25
>
> Perhaps; although that is perhaps assuming the end result.
> If you don't like "approximate" how about "more abstract"?
>
> Gord.
>
> Achim Bauer wrote:
>> Hi Gordon,
>>
>> since models naturally are approximate, I would suggest in stead of
>> "...approximate models for analog blocks"
>> to evtl. use
>> "...real-valued functional or signalflow models for
>> analog/mixed-signal blocks"
>>
>> Achim
>>
>>
>> -----Ursprüngliche Nachricht-----
>> Von: owner-sv-dc@eda.org [mailto:owner-sv-dc@eda.org] Im Auftrag von
>> Gordon Vreugdenhil
>> Gesendet: Dienstag, 25. Mai 2010 16:08
>> An: Havlicek John-R8AAAU
>> Cc: sv-dc@eda.org
>> Betreff: Re: SV-DC meeting 2010-05-25
>>
>> I have two minor suggestions on the proposed scope document.
>>
>> I'd reword:
>>
>> It is expected that these features can exist in SystemVerilog
>> without a SystemVerilog/Verilog-AMS merger.
>>
>> as
>>
>> It is expected that these features can exist in SystemVerilog
>> without requiring a merge of the SystemVerilog and Verilog-AMS
>> standards.
>>
>> And then for:
>>
>> The primary use case motivating this work is the need for
>> high speed AMS models.
>>
>> I would say:
>>
>> The primary use case motivating this work is the need for
>> high speed simulation of approximate models for analog blocks.
>>
>> "High speed AMS" has "analog mixed-signal" which may be a bit
>> misleading in terms of intent.
>>
>> Gord.
>> --
>> --------------------------------------------------------------------
>> Gordon Vreugdenhil 503-685-0808
>> Model Technology (Mentor Graphics) gordonv@model.com
>>
>>
>
> --
> --------------------------------------------------------------------
> Gordon Vreugdenhil 503-685-0808
> Model Technology (Mentor Graphics) gordonv@model.com
>

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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