RE: [sv-ac] function with side effect use in assertion

I think the lines you quote make it clear that this code is considered non-compliant with the standard, and thus will cause an error with tools that enforce compliance. From section 1.5 of p1800-2009:

The terminology conventions used throughout this standard are as follows:
- The word shall is used to indicate mandatory requirements strictly to be followed in order to
conform to the standard and from which no deviation is permitted (shall equals is required to).
- The word should is used to indicate that among several possibilities one is recommended as
particularly suitable, without mentioning or excluding others; or that a certain course of action is
preferred but not necessarily required; or that (in the negative form) a certain course of action is
deprecated but not prohibited (should equals is recommended that).
- The word may is used to indicate a course of action permissible within the limits of the standard
(may equals is permitted to).
- The word can is used for statements of possibility and capability, whether material, physical, or
causal (can equals is able to).

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Daniel Mlynek
Sent: Wednesday, January 26, 2011 3:21 AM
To: sv-ac@eda.org
Subject: [sv-ac] function with side effect use in assertion

I have doubts about below LRM statement. I'm not sure is "shall" used here means that non-automatic function should trigger an error or does it only mean that this is not good idea to use such functions in assertion
Expressions are allowed to include function calls, but the following semantic restrictions are imposed:
- Functions that appear in expressions shall not contain output or ref arguments (const ref is
allowed).
- Functions shall be automatic (or preserve no state information) and have no side effects.

Summarizing my question is - is below code legal or not:?

module top;
    int k,l;
    function int func1();
        $display(k,l);
        k++;l++;
        return k;
    endfunction

    property p1;
        @(posedge clk) func1()!=3; //func1 has side effect and is not automatic
    endproperty

    as1:assert property(p1);

    bit clk;
    initial repeat(10) #5 clk=~clk;
endmodule

DANiel

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